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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7730/ad7730l one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 bridge transducer adc functional block diagram key features resolution of 230,000 counts (peak-to-peak) offset drift: 5 nv/ 8 c gain drift: 2 ppm/ 8 c line frequency rejection: >150 db buffered differential inputs programmable filter cutoffs specified for drift over time operates with reference voltages of 1 v to 5 v additional features two-channel programmable gain front end on-chip dac for offset/tare removal fast step? mode ac or dc excitation single supply operation applications weigh scales pressure measurement general description the ad7730 is a complete analog front end for weigh-scale and pressure measurement applications. the device accepts low- level signals directly from a transducer and outputs a serial digital word. the input signal is applied to a proprietary pro- grammable gain front end based around an analog modulator. fast step is a trademark of analog devices, inc. sigma- delta modulator ad7730 6-bit dac serial interface and control logic register bank clock generation programmable digital filter sigma-delta a/d converter buffer pga 100na agnd 100na av dd vbias ain1(+) ain1(C) ain2(+)/d1 ain2(C)/d0 acx acx standby sync mclk in mclk out sclk cs din dout reset rdy pol dgnd agnd av dd dv dd ref in(C) ref in(+) mux reference detect ac excitation clock calibration microcontroller + +/C the modulator output is processed by a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time. the part features two buffered differential programmable gain analog inputs as well as a differential reference input. the part operates from a single +5 v supply. it accepts four unipolar analog input ranges: 0 mv to +10 mv, +20 mv, +40 mv and +80 mv and four bipolar ranges: 10 mv, 20 mv, 40 mv and 80 mv. the peak-to-peak resolution achievable directly from the part is 1 in 230,000 counts. an on-chip 6-bit dac allows the removal of tare voltages. clock signals for synchro- nizing ac excitation of the bridge are also provided. the serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. the ad7730 contains self-calibration and system calibration options, and features an offset drift of less than 5 nv/ c and a gain drift of less than 2 ppm/ c. the ad7730 is available in a 24-pin plastic dip, a 24-lead soic and 24-lead tssop package. the ad7730l is available in a 24-lead soic and 24-lead tssop package. note the description of the functions and operation given in this data sheet apply to both the ad7730 and ad7730l. specifications and performance parameters differ for the parts. specifications for the ad7730l are outlined in appendix a.
C2C rev. a parameter b version 1 units conditions/comments static performance (chp = 1) no missing codes 2 24 bits min output noise and update rates 2 see tables i & ii integral nonlinearity 18 ppm of fsr max offset error 2 see note 3 offset error and offset drift refer to both offset drift vs. temperature 2 5 nv/ c typ unipolar offset and bipolar zero errors offset drift vs. time 4 25 nv/1000 hours typ positive full-scale error 2, 5 see note 3 positive full-scale drift vs temp 2, 6, 7 2 ppm of fs/ c max positive full-scale drift vs time 4 10 ppm of fs/1000 hours typ gain error 2, 8 see note 3 gain drift vs. temperature 2, 6, 9 2 ppm/ c max gain drift vs. time 4 10 ppm/1000 hours typ bipolar negative full-scale error 2 see note 3 negative full-scale drift vs. temp 2, 6 2 ppm of fs/ c max power supply rejection 120 db typ measured with zero differential voltage common-mode rejection (cmr) 120 db min at dc. measured with zero differential voltage analog input dc bias current 2 50 na max analog input dc bias current drift 2 100 pa/ c typ analog input dc offset current 2 10 na max analog input dc offset current drift 2 50 pa/ c typ static performance (chp = 0) 2 no missing codes 24 bits min skip = 0 10 output noise and update rates see tables iii & iv integral nonlinearity 18 ppm of fsr max offset error see note 3 offset error and offset drift refer to both offset drift vs. temperature 6 0.5 m v/ c typ unipolar offset and bipolar zero errors offset drift vs. time 4 2.5 m v/1000 hours typ positive full-scale error 5 see note 3 positive full-scale drift vs. temp 6, 7 0.6 m v/ c typ positive full-scale drift vs. time 4 3 m v/1000 hours typ gain error 8 see note 3 gain drift vs. temperature 6, 9 2 ppm/ c typ gain drift vs. time 4 10 ppm/1000 hours typ bipolar negative full-scale error see note 3 negative full-scale drift vs. temp 0.6 m v/ c typ power supply rejection 90 db typ measured with zero differential voltage commo n-mode rejection (cmr) on ain 100 db typ at dc. measured with zero differential voltage cmr on ref in 120 db typ at dc. measured with zero differential voltage analog input dc bias current 60 na max analog input dc bias current drift 150 pa/ c typ analog input dc offset current 30 na max analog input dc offset current drift 100 pa/ c typ analog inputs/reference inputs normal-mode 50 hz rejection 2 88 db min from 49 hz to 51 hz normal-mode 60 hz rejection 2 88 db min from 59 hz to 61 hz common-mode 50 hz rejection 2 120 db min from 49 hz to 51 hz common-mode 60 hz rejection 2 120 db min from 59 hz to 61 hz analog inputs differential input voltage ranges 11 assuming 2.5 v or 5 v reference with hiref bit set appropriately 0 to +10 or 10 mv nom gain = 250 0 to +20 or 20 mv nom gain = 125 0 to +40 or 40 mv nom gain = 62.5 0 to +80 or 80 mv nom gain = 31.25 absolute/common-mode voltage 12 agnd + 1.2 v v min av dd C 0.95 v v max reference input ref in(+) C ref in(C) voltage +2.5 v nom hiref bit of mode register = 0 ref in(+) C ref in(C) voltage +5 v nom hiref bit of mode register = 1 absolute/common-mode voltage 13 agnd C 30 mv v min av dd + 30 mv v max no ref trigger voltage 0.3 v min no ref bit active if v ref below this voltage 0.65 v max no ref bit inactive if v ref above this voltage ad7730Cspecifications (av dd = +5 v, dv dd = +3 v or +5 v; ref in(+) = av dd ; ref in(C) = agnd = dgnd = 0 v; f clk in = 4.9152 mhz. all specifications t min to t max unless otherwise noted.)
C3C rev. a ad7730/ad7730l parameter b version 1 units conditions/comments logic inputs input current 10 m a max all inputs except sclk and mclk in v inl , input low voltage 0.8 v max dv dd = +5 v v inl , input low voltage 0.4 v max dv dd = +3 v v inh , input high voltage 2.0 v min sclk only (schmitt triggered input) v t+ 1.4/3 v min to v max dv dd = +5 v v t+ 1/2.5 v min to v max dv dd = +3 v v tC 0.8/1.4 v min to v max dv dd = +5 v v tC 0.4/1.1 v min to v max dv dd = +3 v v t+ C v tC 0.4/0.8 v min to v max dv dd = +5 v v t+ C v tC 0.4/0.8 v min to v max dv dd = +3 v mclk in only v inl , input low voltage 0.8 v max dv dd = +5 v v inl , input low voltage 0.4 v max dv dd = +3 v v inh , input high voltage 3.5 v min dv dd = +5 v v inh , input high voltage 2.5 v min dv dd = +3 v logic outputs (including mclk out) v ol , output low voltage i sink = 800 m a except for mclk out 14 ; 0.4 v max v dd 15 = +5 v v ol , output low voltage i sink = 100 m a except for mclk out 14 ; 0.4 v max v dd 15 = +3 v v oh , output high voltage i source = 200 m a except for mclk out 14 ; 4.0 v min v dd 15 = +5 v v oh , output high voltage i source = 100 m a except for mclk out 14 ; v dd C 0.6 v v min v dd 15 = +3 v floating state leakage current 10 m a max floating state output capacitance 2 6 pf typ transducer burnout ain1(+) current C100 na nom ain1(C) current 100 na nom initial tolerance @ 25 c 10 % typ drift 2 0.1 %/ c typ offset (tare) dac resolution 6 bit lsb size 2.3/2.6 mv min/mv max 2.5 mv nominal with 5 v reference (ref in/2000) dac drift 16 2.5 ppm/ c max dac drift vs. time 4, 16 25 ppm/1000 hours typ differential linearity C0.25/+0.75 lsb max guaranteed monotonic system calibration positive full-scale calibration limit 17 1.05 fs v max fs is the nominal full-scale voltage (10 mv, 20 mv, 40 mv or 80 mv) negative full-scale calibration limit 17 C1.05 fs v max offset calibration limit 18 C1.05 fs v max input span 17 0.8 fs v min 2.1 fs v max power requirements power supply voltages av dd C agnd voltage +4.75 to +5.25 v min to v max dv dd voltage +2.7 to +5.25 v min to v max with agnd = 0 v power supply currents external mclk. digital i/ps = 0 v or dv dd av dd current (normal mode) 10.3 ma max all input ranges except 0 mv to +10 mv and 10 mv av dd current (normal mode) 22.3 ma max input ranges of 0 mv to +10 mv and 10 mv only dv dd current (normal mode) 1.3 ma max dv dd of 2.7 v to 3.3 v dv dd current (normal mode) 2.7 ma max dv dd of 4.75 v to 5.25 v av dd + dv dd current (standby mode) 25 m a max typically 10 m a. external mclk in = 0 v or dv dd power dissipation av dd = dv dd = +5 v. digital i/ps = 0 v or dv dd normal mode 65 mw max all input ranges except 0 mv to +10 mv and 10 mv 125 mw max input ranges of 0 mv to +10 mv and 10 mv only standby mode 125 m w max typically 50 m w. external mclk in = 0 v or dv dd
ad7730/ad7730l C4C rev. a notes 1 1 temperature range: C40 c to +85 c. 1 2 sample tested during initial release. 1 3 the offset (or zero) numbers with chp = 1 are typically 3 m v precalibration. internal zero-scale calibration reduces this by about 1 m v. offset numbers with chp = 0 can be up to 1 mv precalibration. internal zero-scale calibration reduces this to 2 m v typical. system zero-scale calibration reduces offset numbers with chp = 1 and chp = 0 to the order of the noise. gain errors can be up to 3000 ppm precalibration with chp = 0 and chp = 1. performing internal full-scale calibrations o n the 80 mv range reduces the gain error to less than 100 ppm for the 80 mv and 40 mv ranges, to about 250 ppm for the 20 mv range and to about 500 ppm on the 10 mv range. system ful l-scale calibration reduces this to the order of the noise. positive and negative full-scale errors can be calculated from the offset and gain errors. 1 4 these numbers are generated during life testing of the part. 1 5 positive full-scale error includes offset errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. see terminology. 1 6 recalibration at any temperature will remove these errors. 1 7 full-scale drift includes offset drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar i nput ranges. 1 8 gain error is a measure of the difference between the measured and the ideal span between any two points in the transfer functi on. the two points used to calculate the gain error are positive full scale and negative full scale. see terminology. 1 9 gain error drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 10 no missing codes performance with chp = 0 and skip = 1 is reduced below 24 bits for sf words lower than 180 decimal. 11 the analog input voltage range on the ain1(+) and ain2(+) inputs is given here with respect to the voltage on the ain1(C) and a in2(C) inputs respectively. 12 the common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 13 the common-mode voltage range on the reference input pair (ref in(+) and ref in(C)) applies provided the absolute input voltage specification is obeyed. 14 these logic output levels apply to the mclk out output only when it is loaded with a single cmos load. 15 v dd refers to dv dd for all logic outputs expect d0, d1, acx and acx where it refers to av dd . in other words, the output logic high for these four outputs is determined by av dd . 16 this number represents the total drift of the channel with a zero input and the dac output near full scale. 17 after calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. if the input is less tha n negative full scale, the device outputs all 0s. 18 these calibration and span limits apply provided the absolute input voltage specification is obeyed. the offset calibration lim it applies to both the unipolar zero point and the bipolar zero point. specifications subject to change without notice. timing characteristics 1, 2 limit at t min to t max parameter (b version) units conditions/comments master clock range 1 mhz min for specified performance 5 mhz max t 1 50 ns min sync pulsewidth t 2 50 ns min reset pulsewidth read operation t 3 0 ns min rdy to cs setup time t 4 0 ns min cs falling edge to sclk active edge setup time 3 t 5 4 0 ns min sclk active edge to data valid delay 3 60 ns max dv dd = +4.75 v to +5.25 v 80 ns max dv dd = +2.75 v to +3.3 v t 5a 4, 5 0 ns min cs falling edge to data valid delay 60 ns max dv dd = +4.75 v to +5.25 v 80 ns max dv dd = +2.7 v to +3.3 v t 6 100 ns min sclk high pulsewidth t 7 100 ns min sclk low pulsewidth t 8 0 ns min cs rising edge to sclk inactive edge hold time 3 t 9 6 10 ns min bus relinquish time after sclk inactive edge 3 80 ns max t 10 100 ns max sclk active edge to rdy high 3, 7 write operation t 11 0 ns min cs falling edge to sclk active edge setup time 3 t 12 30 ns min data valid to sclk edge setup time t 13 25 ns min data valid to sclk edge hold time t 14 100 ns min sclk high pulsewidth t 15 100 ns min sclk low pulsewidth t 16 0 ns min cs rising edge to sclk edge hold time notes 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of d v dd ) and timed from a voltage level of 1.6 v. 2 see figures 18 and 19. 3 sclk active edge is falling edge of sclk with pol = 1; sclk active edge is rising edge of sclk with pol = 0. 4 these numbers are measured with the load circuit of figure 1 and defined as the time required for the output to cross the v ol or v oh limits. 5 this specification only comes into play if cs goes low while sclk is low (pol = 1) or if cs goes low while sclk is high (pol = 0). it is primarily required for interfacing to dsp machines. 6 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the tim ing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 rdy returns high after the first read from the device after an output update. the same data can be read again, if required, while rdy is high, although care should be taken that subsequent reads do not occur close to the next output update. (av dd = +4.75 v to +5.25 v; dv dd = +2.7 v to +5.25 v; agnd = dgnd = 0 v; f clk in = 4.9152 mhz; input logic 0 = 0 v, logic 1 = dv dd unless otherwise noted).
ad7730/ad7730l rev. a C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7730 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* (t a = +25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . C5 v to +0.3 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . . C2 v to +5 v analog input voltage to agnd . . . . C0.3 v to av dd + 0.3 v reference input voltage to agnd . . C0.3 v to av dd + 0.3 v ain/ref in current (indefinite) . . . . . . . . . . . . . . . . 30 ma digital input voltage to dgnd . . . . C0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . C0.3 v to dv dd + 0.3 v output voltage (acx, acx , d0, d1) to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to av dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c ordering guide temperature package package model range description options ad7730bn C40 c to +85 c plastic dip n-24 ad7730br C40 c to +85 c small outline r-24 ad7730bru C40 c to +85 c thin shrink small outline ru-24 eval-ad7730eb evaluation board ad7730lbr C40 c to +85 c small outline r-24 ad7730lbru C40 c to +85 c thin shrink small outline ru-24 eval-ad7730leb evaluation board plastic dip package, power dissipation . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . 105 c/w lead temperature (soldering, 10 sec) . . . . . . . +260 c tssop package, power dissipation . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . 128 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220 c soic package, power dissipation . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. to output pin 50pf i sink (800 m a at dv dd = +5v 100 m a at dv dd = +3v) +1.6v i source (200 m a at dv dd = +5v 100 m a at dv dd = +3v) figure 1. load circuit for access time and bus relinquish time warning! esd sensitive device
ad7730/ad7730l C6C rev. a figure 2. detailed functional block diagram sigma- delta modulator ad7730 6-bit dac serial interface and control logic register bank clock generation programmable digital filter sigma-delta a/d converter buffer pga agnd av dd vbias ain1(+) ain1(C) ain2(+)/d1 ain2(C)/d0 acx acx standby sync mclk in mclk out sclk cs din dout reset rdy pol dgnd agnd av dd dv dd ref in(C) ref in(+) mux reference detect ac excitation clock calibration microcontroller + register bank thirteen registers control all functions on the part and provide status information and conversion results see page 11 standby mode the standby mode reduces power consumption to 5 m a see page 33 clock oscillator circuit the clock source for the part can be provided by an externally-applied clock or by connecting a crystal or ceramic resonator across the clock pins see page 32 serial interface spi*-compatible or dsp- compatible serial interface which can be operated from just three wires. all functions on the part can be accessed via the serial interface see page 35 offset/tare dac allows a programmed voltage to be either added or subtracted from the analog input signal before it is applied to the pga see page 24 output drivers the second analog input channel can be reconfigured to become two output digital port lines which can be programmed over the serial interface see page 33 ac excitation for ac-excited bridge applications, the acx outputs provide signals that can be used to switch the polarity of the bridge excitation voltage see page 41 analog multiplexer a two-channel differential multiplexer switches one of the two differential input channels to the buffer amplifier. the multiplexer is controlled via the serial interface see page 24 sigma delta adc the sigma delta architecture ensures 24 bits no missing codes. the entire sigma delta. adc can be chopped to remove drift errors see page differential reference the reference input to the part is differential and facilitates ratiometric operation. the reference voltage can be selected to be nominally +2.5v or +5v see page 25 programmable digital filter two stage filter that allows programming of output update rate and settling time and which has a fast step mode (see figure 3) see page 26 sigma-delta adc the sigma-delta architecture ensures 24 bits no missing codes. the entire sigma-delta adc can be chopped to remove drift errors see page 26 programmable gain amplifier the programmable gain amplifier allows four unipolar and four bipolar input ranges from +10mv to +80mv see page 24 buffer amplifier the buffer amplifier presents a high impedance input stage for the analog inputs allowing significant external source impedances see page 24 burnout currents two 100na burnout currents allow the user to easily detect if a transducer has burnt out or gone open-circuit see page 25 +/C *spi is a trademark of motorola , inc.
ad7730/ad7730l rev. a C7C figure 3. signal processing chain pin configuration pin function descriptions pin no. mnemonic function 1 sclk serial clock. schmitt-triggered logic input. an external serial clock is applied to this input to transfer serial data to or from the ad7730. this serial clock can be a continuous clock with all data transmitted in a con- tinuous train of pulses. alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ad7730 in smaller batches of data. 2 mclk in master clock signal for the device. this can be provided in the form of a crystal/resonator or external clock. a crystal/resonator can be tied across the mclk in and mclk out pins. alternatively, the mclk in pin can be driven with a cmos-compatible clock and mclk out left unconnected. the ad7730 is specified with a clock input frequency of 4.9152 mhz while the ad7730l is specified with a clock input frequency of 2.4576 mhz. sclk mclk in dgnd dv dd sync v bias rdy cs mclk out pol din dout agnd av dd acx ain1(+) standby 14 1 2 24 23 5 6 7 20 19 18 3 4 22 21 8 17 9 16 10 15 11 top view (not to scale) 12 13 ad7730 reset ref in(C) ref in(+) ain1(C) ain2(+)/d1 ain2(C)/d0 acx pga + sigma-delta modulator sinc 3 filter chop 22-tap fir filter faststep filter chop input chopping the analog input to the part can be chopped. in chopping mode, with ac excitation disabled, the input chopping is internalto the device. in chopping mode, with ac excitation enabled, the chopping is assumed to be performed external to the part and no internal input chopping is performed. the input chopping can be disabled, if desired. see page 26 analog input digital output sinc 3 filter the first stage of the digital filtering on the part is the sinc 3 filter. the output update rate and bandwidth of this filter can be programmed. in skip mode, the sinc 3 filter is the only filtering performed on the part. see page 26 buffer skip mode in skip mode, there is no second stage of filtering on the part. the sinc 3 filter is the only filtering performed on the part. see page 29 skip output scaling 22-tap fir filter in normal operating mode, the second stage of the digital filtering on the part is a fixed 22-tap fir filter. in skip mode, this fir filter is bypassed. when faststep? mode is enabled and a step input is detected, the second stage filtering is performed by the filter until the output of this filter has fully settled. see page 27 output scaling the output word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result. see page 29 faststep filter when faststep mode is enabled and a step change on the input has been detected, the second stage filtering is performed by the faststep filter until the fir filter has fully settled. see page 29 output chopping the output of the first stage of filtering on the part can be chopped. in chopping mode, regardless of whether ac excitation is enabled or disabled, the output chopping is performed. the chopping can be disabled, if desired. see page 26 pga + sigma-delta modulator the programmable gain capability of the part is incorporated around the sigma-delta modulator. the modulator provides a high- frequency 1-bit data stream to the digital filter. see page 26 buffer the input signal is buffered on-chip before being applied to the sampling capacitor of the sigma-delta modulator. this isolates the sampling capacitor charging currents from the analog input pins. see page 24
ad7730/ad7730l C8C rev. a pin no. mnemonic function 3 mclk out when the master clock for the device is a crystal/resonator, the crystal/resonator is connected between mclk in and mclk out. if an external clock is applied to the mclk in, mclk out provides an inverted clock sig- nal. this clock can be used to provide a clock source for external circuits and mclk out is capable of driving one cmos load. if the user does not require it, mclk out can be turned off with the clkdis bit of the mode register. this ensures that the part is not burning unnecessary power driving capacitance on the mclk out pin. 4 pol clock polarity. logic input. this determines the polarity of the serial clock. if the active edge for the proces- sor is a high-to-low sclk transition, this input should be low. in this mode, the ad7730 puts out data on the data out line in a read operation on a low-to-high transition of sclk and clocks in data from the data in line in a write operation on a high-to-low transition of sclk. in applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle low between data transfers. if the active edge for the processor is a low-to-high sclk transition, this input should be high. in this mode, the ad7730 puts out data on the data out line in a read operation on a high-to-low transi- tion of sclk and clocks in data from the data in line in a write operation on a low-to-high transition of sclk. in applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle high between data transfers. 5 sync logic input that allows for synchronization of the digital filters and analog modulators when using a number of ad7730s. while sync is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state. sync does not affect the digital interface but does reset rdy to a high state if it is low. while sync is asserted, the mode bits may be set up for a subsequent operation which will commence when the sync pin is deasserted. 6 reset logic input. active low input that resets the control logic, interface logic, digital filter, analog modulator and all on-chip registers of the part to power-on status. effectively, everything on the part except for the clock oscillator is reset when the reset pin is exercised. 7v bias analog output. this analog output is an internally-generated voltage used as an internal operating bias point. this output is not for use external to the ad7730 and it is recommended that the user does not connect any- thing to this pin. 8 agnd ground reference point for analog circuitry. 9av dd analog positive supply voltage. the av dd to agnd differential is 5 v nominal. 10 ain1(+) analog input channel 1. positive input of the differential, programmable-gain primary analog input pair. the differential analog input ranges are 0 mv to +10 mv, 0 mv to +20 mv, 0 mv to +40 mv and 0 mv to +80 mv in unipolar mode, and 10 mv, 20 mv, 40 mv and 80 mv in bipolar mode. 11 ain1(C) analog input channel 1. negative input of the differential, programmable gain primary analog input pair. 12 ain2(+)/d1 analog input channel 2 or digital output 1. this pin can be used either as part of a second analog input channel or as a digital output bit as determined by the den bit of the mode register. when selected as an analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. the analog input ranges are 0 mv to +10 mv, 0 mv to +20 mv, 0 mv to +40 mv and 0 mv to +80 mv in unipo- lar mode and 10 mv, 20 mv, 40 mv and 80 mv in bipolar mode. when selected as a digital output, this output can programmed over the serial interface using bit d1 of the mode register. 13 ain2(C)/d0 analog input channel 2 or digital output 0. this pin can be used either as part of a second analog input channel or as a digital output bit as determined by the den bit of the mode register. when selected as an analog input, it is the negative input of the differential, programmable-gain secondary analog input pair. when selected as a digital output, this output can programmed over the serial interface using bit d0 of the mode register. 14 ref in(+) reference input. positive terminal of the differential reference input to the ad7730. ref in(+) can lie anywhere between av dd and agnd. the nominal reference voltage (the differential voltage between ref in(+) and ref in(C)) should be +5 v when the hiref bit of the mode register is 1 and +2.5 v when the hiref bit of the mode register is 0. 15 ref in(C) reference input. negative terminal of the differential reference input to the ad7730. the ref in(C) poten- tial can lie anywhere between av dd and agnd. 16 acx digital output. provides a signal that can be used to control the reversing of the bridge excitation in ac- excited bridge applications. when acx is high, the bridge excitation is taken as normal and when acx is low, the bridge excitation is reversed (chopped). if ac = 0 (ac mode turned off) or chp = 0 (chop mode turned off), the acx output remains high. 17 acx digital output. provides a signal that can be used to control the reversing of the bridge excitation in ac- excited bridge applications. this output is the complement of acx. in ac mode, this means that it toggles in anti-phase with acx . if ac = 0 (ac mode turned off) or chp = 0 (chop mode turned off), the acx output remains low. when toggling, it is guaranteed to be nonoverlapping with acx. the non-overlap interval, when both acx and acx are low, is one master clock cycle.
ad7730/ad7730l rev. a C9C pin no. mnemonic function 18 standby logic input. taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 5 m a range. the on-chip registers retain all their values when the part is in standby mode. 19 cs chip select. active low logic input used to select the ad7730. with this input hardwired low, the ad7730 can operate in its three-wire interface mode with sclk, din and dout used to interface to the device. cs can be used to select the device in systems with more than one device on the serial bus or as a frame synchro- nization signal in communicating with the ad7730. 20 rdy logic output. used as a status output in both conversion mode and calibration mode. in conversion mode, a logic low on this output indicates that a new output word is available from the ad7730 data register. the rdy pin will return high upon completion of a read operation of a full output word. if no data read has taken place after an output update, the rdy line will return high prior to the next output update, remain high while the update is taking place and return low again. this gives an indication of when a read operation should not be initiated to avoid initiating a read from the data register as it is being updated. in calibration mode, rdy goes high when calibration is initiated and it returns low to indicate that calibration is complete. a number of different events on the ad7730 set the rdy high and these are outlined in table xviii. 21 dout serial data output with serial data being read from the output shift register on the part. this output shift register can contain information from the calibration registers, mode register, status register, filter register, dac register or data register, depending on the register selection bits of the communications register. 22 din serial data input with serial data being written to the input shift register on the part. data from this input shift register is transferred to the calibration registers, mode register, communications register, dac register or filter registers depending on the register selection bits of the communications register. 23 dv dd digital supply voltage, +3 v or +5 v nominal. 24 dgnd ground reference point for digital circuitry. terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the end- points of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transi- tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 lsb above the last code transition (111 . . . 110 to 111 . . . 111). the error is expressed as a percentage of full scale. positive full-scale error positive full-scale error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal ain(+) voltage (ain(C) + v ref /gain C 3/2 lsbs). it applies to both unipolar and bipolar analog input ranges. positive full-scale error is a summation of offset error and gain error. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal ain(+) voltage (ain(C) + 0.5 lsb) when oper- ating in the unipolar mode. bipolar zero error this is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal ain(+) voltage (ain(C) C 0.5 lsb) when o perating in the bipolar mode. gain error this is a measure of the span error of the adc. it is a measure of the difference between the measured and the ideal span be- tween any two points in the transfer function. the two points used to calculate the gain error are full scale and zero scale. bipolar negative full-scale error this is the deviation of the first code transition from the ideal ain(+) voltage (ain(C) C v ref /gain + 0.5 lsb) when operat- ing in the bipolar mode. negative full-scale error is a summation of zero error and gain error. positive full-scale overrange positive full-scale overrange is the amount of overhead avail- able to handle input voltages on ain(+) input greater than ain(C) + v ref /gain (for example, noise peaks or excess volt- ages due to system gain errors in system calibration routines) with- out introducing errors due to overloading the analog modulator or overflowing the digital filter. negative full-scale overrange this is the amount of overhead available to handle voltages on ain(+) below ain(C) C v ref /gain without overloading the analog modulator or overflowing the digital filter. offset calibration range in the system calibration modes, the ad7730 calibrates its offset with respect to the analog input. the offset calibration range specification defines the range of voltages the ad7730 can accept and still accurately calibrate offset. full-scale calibration range this is the range of voltages that the ad7730 can accept in the system calibration mode and still calibrate full scale correctly. input span in system calibration schemes, two voltages applied in sequence to the ad7730s analog input define the analog input range. the input span specification defines the minimum and maxi- mum input voltages, from zero to full scale, the ad7730 can accept and still accurately calibrate gain.
ad7730/ad7730l C10C rev. a output noise and resolution specification the ad7730 can be programmed to operate in either chop mode or nonchop mode. the chop mode can be enabled in ac-excited or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. t hese options are discussed in more detail in later sections. the chop mode has the advantage of lower drift numbers and better noise im- munity, but the noise is approximately 20% higher for a given C3 db frequency and output data rate. it is envisaged that the ma jority of weigh-scale users of the ad7730 will operate the part in chop mode to avail themselves of the excellent drift performance an d noise immunity when chopping is enabled. the following tables outline the noise performance of the part in both chop and noncho p modes over all input ranges for a selection of output rates. settling time refers to the time taken to get an output that is 10 0% settled to new value. output noise (chp = 1) this mode is the primary mode of operation of the device. table i shows the output rms noise for some typical output update rat es and C3 db frequencies for the ad7730 when used in chopping mode (chp of filter register = 1) with a master clock frequency of 4.9152 mhz. these numbers are typical and are generated at a differential analog input voltage of 0 v. the output update rate i s selected via the sf0 to sf11 bits of the filter register. table ii, meanwhile, shows the output peak-to-peak resolution in coun ts for the same output update rates. the numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 lsb). it is important to note that the numbers in table ii represent the resolution for which there will be no code flicker wit hin a six-sigma limit. they are not calculated based on rms noise, but on peak-to-peak noise. the numbers are generated for the bipolar input ranges. when the part is operated in unipolar mode, the output noise will be th e same as the equivalent bipolar input range. as a result, the numbers in table i will remain the same for unipolar ranges while the numbers in table ii will change. to calculate the numbers for table ii for unipolar input ranges simply divide the peak-to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits. table i. output noise vs. input range and update rate (chp = 1) typical output rms noise in nv output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 50 hz 1.97 hz 2048 460 ms 60 ms 115 75 55 40 100 hz 3.95 hz 1024 230 ms 30 ms 155 105 75 60 150 hz 5.92 hz 683 153 ms 20 ms 200 135 95 70 200 hz* 7.9 hz 512 115 ms 15 ms 225 145 100 80 400 hz 15.8 hz 256 57.5 ms 7.5 ms 335 225 160 110 *power-on default table ii. peak-to-peak resolution vs. input range and update rate (chp = 1) peak-to-peak resolution in counts (bits) output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 50 hz 1.97 hz 2048 460 ms 60 ms 230k (18) 175k (17.5) 120k (17) 80k (16.5) 100 hz 3.95 hz 1024 230 ms 30 ms 170k (17.5) 125k (17) 90k (16.5) 55k (16) 150 hz 5.92 hz 683 153 ms 20 ms 130k (17) 100k (16.5) 70k (16) 45k (15.5) 200 hz* 7.9 hz 512 115 ms 15 ms 120k (17) 90k (16.5) 65k (16) 40k (15.5) 400 hz 15.8 hz 256 57.5 ms 7.5 ms 80k (16.5) 55k (16) 40k (15.5) 30k (15) *power-on default output noise (chp = 0) table iii shows the output rms noise for some typical output update rates and C3 db frequencies for the ad7730 when used in non - chopping mode (chp of filter register = 0) with a master clock frequency of 4.9152 mhz. these numbers are typical and are gen- erated at a differential analog input voltage of 0 v. the output update rate is selected via the sf0 to sf11 bits of the filter register. table iv, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. the numbers in bracke ts are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 lsb). it is important to note that the numbers in table iv represent the resolution for which there will be no code flicker within a six-sigma limit. they are not calculated based on rms noise, but on peak-to-peak noise. the numbers are generated for the bipolar input ranges. when the part is operated in unipolar mode, the output noise will be th e same as the equivalent bipolar input range. as a result, the numbers in table iii will remain the same for unipolar ranges whil e the numbers in table iv will change. to calculate the number for table iv for unipolar input ranges simply divide the peak-to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
ad7730/ad7730l rev. a C11C table iii. output noise vs. input range and update rate (chp = 0) typical output rms noise in nv output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 150 hz 5.85 hz 2048 166 ms 26.6 ms 160 110 80 60 200 hz 7.8 hz 1536 125 ms 20 ms 190 130 95 75 300 hz 11.7 hz 1024 83.3 ms 13.3 ms 235 145 100 80 600 hz 23.4 hz 512 41.6 ms 6.6 ms 300 225 135 110 1200 hz 46.8 hz 256 20.8 ms 3.3 ms 435 315 210 150 table iv. peak-to-peak resolution vs. input range and update rate (chp = 0) peak-to-peak resolution in counts (bits) output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 150 hz 5.85 hz 2048 166 ms 26.6 ms 165k (17.5) 120k (17) 80k (16.5) 55k (16) 200 hz 7.8 hz 1536 125 ms 20 ms 140k (17) 100k (16.5) 70k (16) 45k (15.5) 300 hz 11.7 hz 1024 83.3 ms 13.3 ms 115k (17) 90k (16.5) 65k (16) 40k (15.5) 600 hz 23.4 hz 512 41.6 ms 6.6 ms 90k (16.5) 60k (16) 50k (15.5) 30k (15) 1200 hz 46.8 hz 256 20.8 ms 3.3 ms 60k (16) 43k (15.5) 32k (15) 20k (14.5) on-chip registers the ad7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. these registers are summa rized in figure 4 and in table v and described in detail in the following sections. communications register status register data register mode register filter register dac register offset register (x3) gain register (x3) test register rs2 rs1 rs0 din dout dout dout dout dout dout dout dout din din din din din din din dout register select decoder figure 4. register overview
ad7730/ad7730l C12C rev. a table v. summary of on-chip registers power-on/reset register name type size default value function communications write only 8 bits not applicable all operations to other registers are initiated through register the communications register. this controls whether subsequent operations are read or write operations and also selects the register for that subsequent operation. most subsequent operations return con- trol to the communications register except for the continuous read mode of operation. status register read only 8 bits cx hex provides status information on conversions, calibra- tions, settling to step inputs, standby operation and the validity of the reference voltage. data register read only 16 bits or 24 bits 000000 hex provides the most up-to-date conversion result from the part. register length can be programmed to be 16 bits or 24 bits. mode register read/write 16 bits 01b0 hex controls functions such as mode of operation, uni- polar/bipolar operation, controlling the function of ain2(+)/d1 and ain2(-)/d0, burnout current, data register word length and disabling of mclk out. it also contains the reference selection bit, the range selection bits and the channel selection bits. filter register read/write 24 bits 200010 hex controls the amount of averaging in the first stage filter, selects the fast step and skip modes and con- trols the ac excitation and chopping modes on the part. dac register read/write 8 bits 20 hex provides control of the amount of correction per- formed by the offset/tare dac. offset register read/write 24 bits 800000 hex contains a 24-bit word which is the offset calibration coefficient for the part. the contents of this register are used to provide offset correction on the output from the digital filter. there are three offset regis- ters on the part and these are associated with the input channels as outlined in table xiii. gain register read/write 24 bits 59aee7 hex contains a 24-bit word which is the gain calibration coefficient for the part. the contents of this register are used to provide gain correction on the output from the digital filter. there are three gain registers on the part and these are associated with the input channels as outlined in table xiii. test register read/write 24 bits 000000 hex controls the test modes of the part which are used when testing the part. the user is advised not to change the contents of this register. wen zero rw1 rw0 zero rs2 rs1 rs0 rdy stdy stby noref ms3 ms2 ms1 ms0 md2 md1 md0 b /u den d1 d0 wl hiref zero rn1 rn0 clkdis bo ch1 ch0 sf11 sf10 sf9 sf8 sf7 sf6 sf5 sf4 sf3 sf2 sf1 sf0 zero zero skip fast zero zero ac chp dl3 dl2 dl1 dl0 zero zero dac5 dac4 dac3 dac2 dac1 dac0
ad7730/ad7730l rev. a C13C communications register (rs2Crs0 = 0, 0, 0) the communications register is an 8-bit write-only register. all communications to the part must start with a write operation t o the communications register. the data written to the communications register determines whether the next operation is a read or write operation, the type of read operation, and to which register this operation takes place. for single-shot read or write op erations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a w rite op- eration to the communications register. this is the default state of the interface, and on power-up or after a reset , the ad7730 is in this default state waiting for a write operation to the communications register. in situations where the interface sequen ce is lost, a write operation of at least 32 serial clock cycles with din high, returns the ad7730 to this default state by resett ing the part. table vi outlines the bit designations for the communications register. cr0 through cr7 indicate the bit location, cr den ot- ing the bits are in the communications register. cr7 denotes the first bit of the data stream. table vi. communications register cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen zero rw1 rw0 zero rs2 rs1 rs0 bit bit location mnemonic description cr7 wen write enable bit. a 0 must be written to this bit so the write operation to the communications register actually takes place. if a 1 is written to this bit, the part will not clock on to subsequent bits in the register. it will stay at this bit location until a 0 is written to this bit. once a 0 is writ- ten to the wen bit, the next seven bits will be loaded to the communications register. cr6 zero a zero must be written to this bit to ensure correct operation of the ad7730. cr5, cr4 rw1, rw0 read/write mode bits. these two bits determine the nature of the subsequent read/write opera- tion. table vii outlines the four options. table vii. read/write mode rw1 rw0 read/write mode 0 0 single write to specified register 0 1 single read of specified register 1 0 start continuous read of specified register 1 1 stop continuous read mode with 0, 0 written to these two bits, the next operation is a write operation to the register specified by bits rs2, rs1, rs0. once the subsequent write operation to the specified register has been com- pleted, the part returns to where it is expecting a write operation to the communications register. with 0,1 written to these two bits, the next operation is a read operation of the register specified by bits rs2, rs1, rs0. once the subsequent read operation to the specified register has been completed, the part returns to where it is expecting a write operation to the communications register. writing 1,0 to these bits, sets the part into a mode of continuous reads from the register speci- fied by bits rs2, rs1, rs0. the most likely registers with which the user will want to use this function are the data register and the status register. subsequent operations to the part will consist of read operations to the specified register without any intermediate writes to the com- munications register. this means that once the next read operation to the specified register has taken place, the part will be in a mode where it is expecting another read from that specified register. the part will remain in this continuous read mode until 30 hex has been written to the communications register. when 1,1 is written to these bits (and 0 written to bits cr3 through cr0), the continuous read mode is stopped and the part returns to where it is expecting a write operation to the communi- cations register. note, the part continues to look at the din line on each sclk edge during continuous read mode to determine when to stop the continuous read mode. therefore, the user must be careful not to inadvertently exit the continuous read mode or reset the ad7730 by writing a series of 1s to the part. the easiest way to avoid this is to place a logic 0 on the din line while the part is in continuous read mode. once the part is in continuous read mode, the user should ensure that an integer multiple of 8 serial clocks should have taken place before attempting to take the part out of continuous read mode.
ad7730/ad7730l C14C rev. a bit bit location mnemonic description cr3 zero a zero must be written to this bit to ensure correct operation of the ad7730. cr2Ccr0 rs2Crs0 register selection bits. rs2 is the msb of the three selection bits. the three bits select which register type the next read or write operation operates upon as shown in table viii. table viii. register selection rs2 rs1 rs0 register 0 0 0 communications register (write operation) 0 0 0 status register (read operation) 0 0 1 data register 0 1 0 mode register 0 1 1 filter register 1 0 0 dac register 1 0 1 offset register 1 1 0 gain register 1 1 1 test register status register (rs2Crs0 = 0, 0, 0); power-on/reset status: cx hex the status register is an 8-bit read-only register. to access the status register, the user must write to the communications re gister selecting either a single-shot read or continuous read mode and load bits rs2, rs1, rs0 with 0, 0, 0. table ix outlines the bit desig- nations for the status register. sr0 through sr7 indicate the bit location, sr denoting the bits are in the status register. sr 7 denotes the first bit of the data stream. figure 5 shows a flowchart for reading from the registers on the ad7730. the number in brackets indicates the power-on/reset default status of that bit. table ix. status register sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) stdy (1) stby (0) noref (0) ms3 (x) ms2 (x) ms1 (x) ms0 (x) bit bit location mnemonic description sr7 rdy ready bit. this bit provides the status of the rdy flag from the part. the status and function of this bit is the same as the rdy output pin. a number of events set the rdy bit high as indi- cated in table xviii. sr6 stdy steady bit. this bit is updated when the filter writes a result to the data register. if the filter is in fast step mode (see filter register section) and responding to a step input, the stdy bit remains high as the initial conversion results become available. the rdy output and bit are set low on these initial conversions to indicate that a result is available. if the stdy is high, however, it indicates that the result being provided is not from a fully settled second-stage fir filter. when the fir filter has fully settled, the stdy bit will go low coincident with rdy . if the part is never placed into its fast step mode, the stdy bit will go low at the first data register read and it is not cleared by subsequent data register reads. a number of events set the stdy bit high as indicated in table xviii. stdy is set high along with rdy by all events in the table except a data register read. sr5 stby standby bit. this bit indicates whether the ad7730 is in its standby mode or normal mode of operation. the part can be placed in its standby mode using the standby input pin or by writing 011 to the md2 to md0 bits of the mode register. the power-on/reset status of this bit is 0 assuming the standby pin is high. sr4 noref no reference bit. if the voltage between the ref in(+) and ref in(C) pins is below 0.3 v, or either of these inputs is open-circuit, the noref bit goes to 1. if noref is active on comple- tion of a conversion, the data register is loaded with all 1s. if noref is active on completion of a calibration, updating of the calibration registers is inhibited. sr3Csr0 ms3Cms0 these bits are for factory use. the power-on/reset status of these bits vary, depending on the factory-assigned number.
ad7730/ad7730l rev. a C15C data register (rs2Crs0 = 0, 0, 1); power on/reset status: 000000 hex the data register on the part is a read-only register which contains the most up-to-date conversion result from the ad7730. fig - ure 5 shows a flowchart for reading from the registers on the ad7730. the register can be programmed to be either 16 bits or 24 b its wide, determined by the status of the wl bit of the mode register. the rdy output and rdy bit of the status register are set low when the data register is updated. the rdy pin and rdy bit will return high once the full contents of the register (either 16 bits or 24 bits) have been read. if the data register has not been read by the time the next output update occurs, the rdy pin and rdy bit will go high for at least 100 t clk in , indicating when a read from the data register should not be initiated to avoid a transfer from the data register as it is being updated. once the updating of the data register has taken place, rdy returns low. if the communications register data sets up the part for a write operation to this register, a write operation must actually ta ke place in order to return the part to where it is expecting a write operation to the communications register (the default state of the inter- face). however, the 16 or 24 bits of data written to the part will be ignored by the ad7730. mode register (rs2Crs0 = 0, 1, 0); power on/reset status: 01b0 hex the mode register is a 16-bit register from which data can be read or to which data can be written. this register configures the operating modes of the ad7730, the input range selection, the channel selection and the word length of the data register. table x outlines the bit designations for the mode register. mr0 through mr15 indicate the bit location, mr denoting the bits ar e in the mode register. mr15 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset defaul t status of that bit. figure 5 shows a flowchart for reading from the registers on the ad7730 and figure 6 shows a flowchart for writ- ing to the registers on the part. table x. mode register mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 md2 (0) md1 (0) md0 (0) b /u (0) den (0) d1 (0) d0 (0) wl (1) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 hiref (1) zero (0) rn1 (1) rn0 (1) clkdis (0) bo (0) ch1 (0) ch0 (0) bit bit location mnemonic description mr15Cmr13 md2Cmd0 mode bits. these three bits determine the mode of operation of the ad7730 as outlined in table xi. the modes are independent, such that writing new mode bits to the mode register will exit the part from the mode in which it is operating and place it in the new requested mode immediately after the mode register write. the function of the mode bits is described in more detail below. table xi. operating modes md2 md1 md0 mode of operation 0 0 0 sync (idle) mode power-on/reset default 0 0 1 continuous conversion mode 0 1 0 single conversion mode 0 1 1 power-down (standby) mode 1 0 0 internal zero-scale calibration 1 0 1 internal full-scale calibration 1 1 0 system zero-scale calibration 1 1 1 system full-scale calibration
ad7730/ad7730l C16C rev. a md2 md1 md0 operating mode 0 0 0 sync (idle) mode. in this mode, the modulator and filter are held in reset mode and the ad7730 is not processing any new samples or data. placing the part in this mode is equivalent to exerting the sync input pin. however, exerting the sync pin does not actually force these mode bits to 0, 0, 0. the part returns to this mode after a calibration or after a conversion in single conversion mode. this is the default condition of these bits after power-on/reset. 0 0 1 continuous conversion mode. in this mode, the ad7730 is continuously processing data and providing conversion results to the data register at the programmed output update rate (as determined by the filter register). for most applications, this would be the normal operating mode of the ad7730. 0 1 0 single conversion mode. in this mode, the ad7730 performs a single conversion, updates the data register, returns to the sync mode and resets the mode bits to 0, 0, 0. the result of the single conversion on the ad7730 in this mode will not be provided until the full settling time of the filter has elapsed. 0 1 1 power-down (standby) mode. in this mode, the ad7730 goes into its power-down or standby state. placing the part in this mode is equivalent to exerting the standby input pin. however, exerting standby does not actually force these mode bits to 0, 1, 1. 1 0 0 zero-scale self-calibration mode. this activates zero-scale self-calibration on the channel selected by ch1 and ch0 of the mode register. this zero-scale self-calibration is performed at the selected gain on internally shorted (zeroed) inputs. when this zero-scale self-calibration is complete, the part updates the contents of the appropriate offset calibration register and returns to sync mode with md2, md1 and md0 returning to 0, 0, 0. the rdy output and bit go high when calibration is initiated and return low when this zero-scale self-calibration is complete to indicate that the part is back in sync mode and ready for further operations. 1 0 1 full-scale self-calibration mode. this activates full-scale self-calibration on the channel selected by ch1 and ch0 of the mode register. this full-scale self-calibration is performed at the selected gain on an internally-generated full-scale signal. when this full-scale self-calibration is complete, the part updates the contents of the appropriate gain calibration register and offset calibration register and returns to sync mode with md2, md1 and md0 returning to 0, 0, 0. the rdy output and bit go high when calibration is initiated and return low when this full-scale self-calibration is complete to indicate that the part is back in sync mode and ready for further operations. 1 1 0 zero-scale system calibration mode. this activates zero scale system calibration on the channel selected by ch1 and ch0 of the mode register. calibration is performed at the selected gain on the input volt- age provided at the analog input during this calibration sequence. this input voltage should remain stable for the duration of the calibration. when this zero-scale system calibration is complete, the part updates the contents of the appropriate offset calibration register and returns to sync mode with md2, md1 and md0 returning to 0, 0, 0. the rdy output and bit go high when calibration is initiated and return low when this zero-scale calibration is complete to indicate that the part is back in sync mode and ready for further operations. 1 1 1 full-scale system calibration mode. this activates full-scale system calibration on the selected input channel. calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. this input voltage should remain stable for the duration of the calibra- tion. when this full-scale system calibration is complete, the part updates the contents of the appropriate gain calibration register and returns to sync mode with md2, md1 and md0 returning to 0, 0, 0. the rdy output and bit go high when calibration is initiated and return low when this full-scale calibra- tion is complete to indicate that the part is back in sync mode and ready for further operations.
ad7730/ad7730l rev. a C17C bit bit location mnemonic description mr12 b /u bipolar/unipolar bit. a 0 in this bit selects bipolar operation and the output coding is 00 . . . 000 for negative full-scale input, 10 . . . 000 for zero input, and 11 . . . 111 for positive full-scale input. a 1 in this bit selects unipolar operation and the output coding is 00 . . . 000 for zero input and 11 . . . 111 for positive full-scale input. mr11 den digital output enable bit. with this bit at 1, the ain2(+)/d1 and ain2(C)/d0 pins assume their digital output functions and the output drivers connected to these pins are enabled. in this mode, the user effectively has two port bits which can be programmed over the serial interface. mr10Cmr9 d1Cd0 digital output bits. these bits determine the digital outputs on the ain2(+)/d1 and ain2(C)/d0 pins, respectively, when the den bit is a 1. for example, a 1 written to the d1 bit of the mode register (with the den bit also a 1) will put a logic 1 on the ain2(+)/d1 pin. this logic 1 will remain on this pin until a 0 is written to the d1 bit (in which case the ain2(+)/d1 pin goes to a logic 0) or the digital output function is disabled by writing a 0 to the den bit. mr8 wl data word length bit. this bit determines the word length of the data register. a 0 in this bit selects 16-bit word length when reading from the data register (i.e., rdy returns high after 16 serial clock cycles in the read operation). a 1 in this bit selects 24-bit word length for the data register. mr7 hiref high reference bit. this bit should be set in accordance with the reference voltage which is being used on the part. if the reference voltage is 5 v, the hiref bit should be set to 1. if the reference voltage is 2.5 v, the hiref bit should be set to a 0. with the hiref bit set correctly for the appropriate applied reference voltage, the input ranges are 0 mv to +10 mv, +20 mv, +40 mv and +80 mv for unipolar operation and 10 mv, 20 mv, 40 mv and 80 mv for bipolar operation. it is possible for a user with a 2.5 v reference to set the hiref bit to a 1. in this case, the part is oper- ating with a 2.5 v reference but assumes it has a 5 v reference. as a result, the input ranges on the part become 0 to +5 mv, +10 mv, +20 mv and +40 mv for unipolar operation and 5 mv, 10 mv, 20 mv and 40 mv for bipolar operation. however, the output noise from the part (in nv) will re- main unchanged so the resolution of the part (in counts) will halve. mr6 zero a zero must be written to this bit to ensure correct operation of the ad7730. mr5Cmr4 rn1Crn0 input range bits. these bits determine the analog input range for the selected analog input. the dif- ferent input ranges are outlined in table xii. the table is valid for a reference voltage of 5 v with the hiref bit at 1, or for a reference voltage of 2.5 v with the hiref bit at a logic 0. table xii. input range selection input range rn1 rn0 b /u bit = 0 b /u bit = 1 0 0 C10 mv to +10 mv 0 mv to +10 mv 0 1 C20 mv to +20 mv 0 mv to +20 mv 1 0 C40 mv to +40 mv 0 mv to +40 mv 1 1 C80 mv to +80 mv 0 mv to +80 mv power-on/reset default note that the input range given in the above table is the range that appears at the input of the pga after the dac offset value has been applied. if the dac adjusts out no offset (dac register is 0010 0000), then this is also the input voltage range at the analog input pins. if, for example, the dac sub- tracts out 50 mv of offset and the part is being operated in bipolar mode with rn1 and rn0 at 0, 0, the actual input voltage range at the analog input is +40 mv to +60 mv. mr3 clkdis master clock disable bit. a 1 in the bit disables the master clock from appearing at the mclk out pin. when disabled, the mclk out pin is forced low. it allows the user the flexibility of using the mclk out as a clock source for other devices in the system or of turning off the mclk out as a power saving feature. when using an external master clock at the mclk in pin, the ad7730 contin- ues to have internal clocks and will convert normally with the clkdis bit active. when using a crystal oscillator or ceramic resonator across the mclk in and mclk out pins, the ad7730 clock is stopped and no conversions take place when the clkdis bit is active.
ad7730/ad7730l C18C rev. a bit bit location mnemonic description mr2 bo burnout current bit. a 1 in this bit activates the burnout currents. when active, the burnout currents connect to the selected analog input pair, one source current to the ain(+) input and one sink current to the ain(C) input. a 0 in this bit turns off the on-chip burnout currents. mr1Cmr0 ch1Cch0 channel selection bits. these bits select the analog input channel to be converted or calibrated as outlined in table xiii. with ch1 at 1 and ch0 at 0, the part looks at the ain1(C) input internally shorted to itself. this can be used as a test method to evaluate the noise performance of the part with no external noise sources. in this mode, the ain1(C) input should be connected to an external voltage within the allowable common-mode range of the part. the offset and gain calibration registers on the part are paired. there are three pairs of calibration registers labelled register pair 0 through regis- ter pair 2. these are assigned to the input channel pairs as outlined in table xiii. table xiii. channel selection input channel pair ch1 ch0 positive input negative input calibration register pair 0 0 ain1(+) ain1(C) register pair 0 0 1 ain2(+) ain2(C) register pair 1 1 0 ain1(C) ain1(C) register pair 0 1 1 ain1(C) ain2(C) register pair 2 filter register (rs2-rs0 = 0, 1, 1); power-on/reset status: 200010 hex the filter register is a 24-bit register from which data can be read or to which data can be written. this register determines the amount of averaging performed by the filter and the mode of operation of the filter. it also sets the chopping mode and the del ay associated with chopping the inputs. table xiv outlines the bit designations for the filter register. fr0 through fr23 indicate the bit location, fr denoting the bits are in the filter register. fr23 denotes the first bit of the data stream. the number in bra ckets indicates the power-on/reset default status of that bit. figure 5 shows a flowchart for reading from the registers on the ad773 0 and figure 6 shows a flowchart for writing to the registers on the part. table xiv. filter register fr23 fr22 fr21 fr20 fr19 fr18 fr17 fr16 sf11 (0) sf10 (0) sf9 (1) sf8 (0) sf7 (0) sf6 (0) sf5 (0) sf4 (0) fr15 fr14 fr13 fr12 fr11 fr10 fr9 fr8 sf3 (0) sf2 (0) sf1 (0) sf0 (0) zero (0) zero (0) skip (0) fast (0) fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 zero (0) zero (0) ac (0) chp (1) dl3 (0) dl2 (0) dl1 (0) dl0 (0) bit bit location mnemonic description fr23Cfr12 sf11Csf0 sinc 3 filter selection bits. the ad7730 contains two filters: a sinc 3 filter and an fir filter. the 12 bits programmed to sf11 through sf0 set the amount of averaging the sinc 3 filter performs. as a result, the number programmed to these 12 bits affects the C3 db frequency and output update rate from the part (see filter architecture section). the allowable range for sf words depends on whether the part is operated with chop on or off and skip on or off. table xv outlines the sf ranges for different setups. all output update rates will be one-half those quoted in table xv for the ad7730l operating with a 2.4576 mhz clock.
ad7730/ad7730l rev. a C19C table xv. sf ranges chop skip sf range output update rate range (assuming 4.9152 mhz clock) 0 0 2048 to 150 150 hz to 2.048 khz 1 0 2048 to 75 50 hz to 1.365 khz 0 1 2048 to 40 150 hz to 7.6 khz 1 1 2048 to 20 50 hz to 5.12 khz bit bit location mnemonic description fr11Cfr10 zero a zero must be written to these bits to ensure correct operation of the ad7730. fr9 skip fir filter skip bit. with a 0 in this bit, the ad7730 performs two stages of filtering before shipping a result out of the filter. the first is a sinc 3 filter followed by a 22-tap fir filter. with a 1 in this bit, the fir filter on the part is bypassed and the output of the sinc 3 is fed directly as the output result of the ad7730s filter (see filter architecture for more details on the filter implementation). fr8 fast fast step mode enable bit. a 1 in this bit enables the fast step mode on the ad7730. in this mode, if a step change on the input is detected, the fir calculation portion of the filter is suspended and replaced by a simple moving average on the output of the sinc 3 filter. initially, two outputs from the sinc 3 filter are used to calculate an ad7730 output. the number of sinc 3 outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to 16) until the stdy bit goes low. when the fir filter has fully settled after a step, the stdy bit will become active and the fir filter is switched back into the processing loop (see filter architec- ture section for more details on the fast step mode). fr7Cfr6 zero a zero must be written to these bits to ensure correct operation of the ad7730. fr5 ac ac excitation bit. if the signal source to the ad7730 is ac-excited, a 1 must be placed in this bit. for dc-excited inputs, this bit must be 0. the ac bit has no effect if chp is 0. with the ac bit at 1, the ad7730 a ssumes that the voltage at the ain(+)/ain(C) and ref in(+)/ref in(C) input terminals are reversed on alternate input sampling cycles (i.e. chopped). note that when the ad7730 is performing internal zero-scale or full-scale calibrations, the ac bit is treated as a 0, i.e., the device performs these self-calibrations with dc excitation. fr4 chp chop enable bit. this bit determines if the chopping mode on the part is enabled. a 1 in this bit location enables chopping on the part. when the chop mode is enabled, the part is effectively chopped at its input and output to remove all offset and offset drift errors on the part. if offset performance with time and temperature are important parameters in the design, it is recom- mended that the user enable chopping on the part. if the input signal is dc-excited, the user has the option of operating the part in either chop or nonchop mode. if the input signal is ac-excited, both the ac bit and the chp bit must be set to 1. the chop rate on the acx and acx signals is one half of the programmed output rate of the part and thus the chopping frequency varies with the programmed output rate. fr3Cfr0 dl3Cdl0 delay selection bits. these four bits program the delay (in modulator cycles) to be inserted after each chop edge when the chp bit is 1. one modulator cycle is mclk in/16 and is 3.25 m s at mclk in = 4.9152 mhz. a delay should only be required when in ac mode. its purpose is to cater for external delays between the switching signals (acx and acx ) and when the analog inputs are actually switched and settled. during the specified number of cycles (between 0 and 15), the modulator is held in reset and the filter does not accept any inputs. if chp = 1, the output rate is (mclk in/ 16 (dl + 3 sf) where dl is the value loaded to bits dl0Cdl3. the chop rate is always one half of the output rate. this chop period takes into account the programmed delay and the fact that the sinc 3 filter must settle every chop cycle. with chp = 0, the output rate is 1/sf.
ad7730/ad7730l C20C rev. a dac register (rs2Crs0 = 1, 0, 0); power on/reset status: 20 hex the dac register is an 8-bit register from which data can either be read or to which data can be written. this register provide s the code for the offset-compensation dac on the part. table xvi outlines the bit designations for the dac register. dr0 through dr7 indicate the bit location, dr denoting the bits are in the dac register. dr7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. figure 5 shows a flowchart for reading from the registers on the ad7730 and figure 6 shows a flowchart for writing to the registers on the part. table xvi. dac register dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 zero (0) zero (0) dac5 (1) dac4 (0) dac3 (0) dac2 (0) dac1 (0) dac0 (0) bit bit location mnemonic description dr7Cdr6 zero a zero must be written to these bits to ensure correct operation of the ad7730. dr5Cdr0 dac5Cdac0 dac selection bits. these bits program the output of the offset dac. the dac is effectively 6 bits with one sign bit (dac5) and five magnitude bits. with dac5 at 1, the dac output subtracts from the analog input before it is applied to the pga. with dac5 at 0, the dac output adds to the analog input before it is applied to the pga. the dac output is given by (v ref /62.5) (d/32) = (v ref /2000) d where d is the decimal equivalent of bits dac4 to dac0. thus, for a 5 v reference applied across the ref in pins, the dac resolution is 2.5 mv and offsets in the range C77.5 mv to +77.5 mv can be removed from the analog input signal before it is applied to the pga. note, that the hiref bit has no effect on the dac range or resolution, it controls the adc range only. offset calibration register (rs2Crs0 = 1, 0, 1); power-on/reset status: 800000 hex the ad7730 contains three 24-bit offset calibration registers, labelled offset calibration register 0 to offset calibration reg - ister 2, to which data can be written and from which data can be read. the three registers are totally independent of each other . the offset calibration register is used in conjunction with the associated gain calibration register to form a register pair. t he calibration register pair used to scale the output is as outlined in table xiii. the offset calibration register is updated aft er an offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the md2, md1, md0 bits of the mode register). during subsequent conversions, the contents of this register are subtracted from the filter output prior to gain scaling being performed on the w ord. figure 5 shows a flowchart for reading from the registers on the ad7730 and figure 6 shows a flowchart for writing to the regis - ters on the part. gain calibration register (rs2Crs0 = 1, 1, 0); power-on/reset status: 593cea the ad7730 contains three 24-bit gain calibration registers, labelled gain calibration register 0 to gain calibration register 2, to which data can be written and from which data can be read. the three registers are totally independent of each other. the gain calibration register is used in conjunction with the associated offset calibration register to form a register pair. the calibration register pair used to scale the output is as outlined in table xiii. the gain calibration register is updated after a gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the md2, md1, md0 bits of the mode register). during subsequent con- versions, the contents of this register are used to scale the number which has already been offset corrected with the offset ca li- bration re gister contents. figure 5 shows a flowchart for reading from the registers on the ad7730 and figure 6 shows a flowchart for writing to the registers on the part. test register (rs2Crs0 = 1, 1, 1); power-on/reset status: 000000hex the ad7730 contains a 24-bit test register to which data can be written and from which data can be read. the contents of this test register are used in testing the device. the user is advised not to change the status of any of the bits in this register from the default (power-on or reset) status of all 0s as the part will be placed in one of its test modes and will not operate correctly . if the part enters one of its test modes, exercising reset or writing 32 successive 1s to the part will exit the ad7730 from the mode and return all register contents to their power-on/reset status. note, if the part is placed in one of its test modes, it may not b e possible to read back the contents of the test register depending on the test mode in which the part has been placed.
ad7730/ad7730l rev. a C21C reading from and writing to the on-chip registers the ad7730 contains a total of thirteen on-chip registers. these registers are all accessed over a three-wire interface. as a r esult, addressing of registers is via a write operation to the topmost register on the part, the communications register. figure 5 sho ws a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access e ach of the registers. figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence an d words to be written to the ad7730. figure 5. flowchart for reading from the ad7730 registers figure 6. flowchart for writing to the ad7730 registers register byte y (hex) communications register 00 data register read only register mode register 02 filter register 03 dac register 04 offset register 05 gain register 06 test register user is advised not to change contents of test register. byte w byte y byte z register (hex) (hex) (hex) status register 10 20 30 data register 11 21 30 mode register 12 22 30 filter register 13 n/a* n/a* dac register 14 n/a* n/a* offset register 15 n/a* n/a* gain register 16 n/a* n/a* test register 17 n/a* n/a* *n/a= not applicable. continuous reads of these registers does not make sense as the register contents would remain the same since they are only changed by a write operation. start write byte w to communications register (see accompanying table) yes read register no write byte y to communications register (see accompanying table) read register yes no write byte z to communications register (see accompanying table) stop continuous read operation? continuous reads of register required? start write byte y to communications register (see accompanying table) write to register end
ad7730/ad7730l C22C rev. a calibration operation summary the ad7730 contains a number of calibration options as outlined pre viously. table xvii summarizes the calibration types, the operations involved and the duration of the operations. there are two methods of determining the end of calibration. the first is to monitor the hardware rdy pin using either interrupt-driven or polling routines. the second method is to do a software poll of the rdy bit in the status register. this can be achieved by setting up the part for continuous reads of the status register once a cal ibra- tion has been initiated. the rdy pin and rdy bit go high on initiating a calibration and return low at the end of the calibration routine. at this time, the md2, md1, md0 bits of the mode register have returned to 0, 0, 0. the fast and skip bits are treated as 0 for the calibration sequence so the full filter is always used for the calibration routines. see calibration section for f ull detail. table xvii. calibration operations md2, md1, duration to rdy duration to rdy calibration type md0 low (chp = 1) low (chp = 0) calibration sequence internal zero-scale 1, 0, 0 22 1/output rate 24 1/output rate calibration on internal shorted input with pga set for selected input range. the ac bit is ignored for this c alibra- tion sequence. the sequence is performed with dc excitation. the offset calibration register for the selected channel is updated at the end of this calibration sequence. for full self- calibration, this calibration should be preceded by an internal full-scale calibration. for applicat ions which require an internal zero-scale and system full-scale calibration, this internal zero-scale calibration should be performed first. internal full-scale 1, 0, 1 44 1/output rate 48 1/output rate calibration on internally-generated input full-scale with pga set for selected input range. the ac bit is ignored for this calibration sequence. the sequence is performed with dc excitation. the gain calibration register for the selected channel is updated at the end of this calibration sequence. it is recommended that internal full-scale calibrations are performed on the 80 mv range, regardless of the subsequent operating range, to optimize the post- calibration gain error. this calibration should be followed by either an internal zero-scale or system zero-scale calibration. this zero-scale calibration should be performed at the operating input range. system zero-scale 1, 1, 0 22 1/output rate 24 1/output rate calibration on externally applied input voltage with pga set for selected input range. the input applied is assumed to be the zero scale of the system. if ac = 1, the system continues to use ac excitation for the duration of the calibration. for full system calibra tion, this system zero- scale calibration should be performed first. for applications which require a system zero-scale and internal full-scale calibration, this calibration should be preceded by the internal full-scale calibration. the offset calibration register for the selected channel is updated at the end of this calibration sequence. system full-scale 1, 1, 1 22 1/output rate 24 1/output rate calibration on externally-applied input voltage with pga set for selected input range. the input applied is assumed to be the full-scale of the system. if ac = 1, the system continues to use ac excitation for the duration of the calibration. this calibration should be preceded by a system zero-scale or internal zero-scale calibration. the gain calibration register for the selected channel is updated at the end of this calibration sequence.
ad7730/ad7730l rev. a C23C circuit description the ad7730 is a sigma-delta a/d converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low-frequency signals such as those in weigh-scale, strain-gage, pressure transducer or temperature measurement applications. it contains a sigma-delta (or charge-balancing) adc, a calibra- tion microcontroller with on-chip static ram, a clock oscillator, a digital filter and a bidirectional serial communications port. the part consumes 13 ma of power supply current with a standby mode which consumes only 25 m a. the part operates from a single +5 v supply. the clock source for the part can be provided via an external clock or by connecting a crystal oscillator or ceramic resonator across the mclk in and mclk out pins. the part contains two programmable-gain fully differential analog input channels. the part handles a total of eight different input ranges which are programmed via the on-chip registers. there are four differential unipolar ranges: 0 mv to +10 mv, 0 mv to +20 mv, 0 mv to +40 mv and 0 mv to +80 mv and four differen- tial bipolar ranges: 10 mv, 20 mv, 40 mv and 80 mv. the ad7730 employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. the sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital informa- tion. a digital low-pass filter processes the output of the sigma- delta modulator and updates the data register at a rate that can be programmed over the serial interface. the output data from the part is accessed over this serial interface. the cutoff frequency and output rate of this filter can be programmed via on-chip registers. the output noise performance and peak-to-peak reso- lution of the part varies with gain and with the output rate as shown in tables i to iv. the analog inputs are buffered on-chip allowing the part to handle significant source impedances on the analog input. this means that external r, c filtering (for noise rejection or rfi reduction) can be placed on the analog inputs if required. both analog channels are differential, with a common-mode voltage range that comes within 1.2 v of agnd and 0.95 v of av dd . the reference input is also differential and the common-mode range here is from agnd to av dd . the part contains a 6-bit dac that is controlled via on-chip registers. this dac can be used to remove tare values of up to 80 mv from the analog input signal range. the resolution on this tare function is 1.25 mv for a +2.5 v reference and 2.5 mv with a +5 v reference. the ad7730 can accept input signals from a dc-excited bridge. it can also handle input signals from an ac-excited bridge by using the ac excitation clock signals (acx and acx ) to switch the supplies to the bridge. acx and acx are nonoverlapping clock signals used to synchronize the external ac supplies that drive the transducer bridge. these acx clocks are demodulated on the ad7730 input. the ad7730 contains a number of hardware and software events that set or reset status flags and bits in registers. table xviii summarizes which blocks and flags are affected by the different events. table xviii. reset events set registers mode filter analog reset serial set rdy set stdy event to default bits reset power-down interface pin/bit bit power-on reset yes 000 yes yes yes yes yes reset pin yes 000 yes no yes yes yes standby pin no as is yes yes no yes yes mode 011 write no 011 yes yes no yes yes sync pin no as is yes no no yes yes mode 000 write no 000 yes no no yes yes conversion or no new initial no no yes yes cal mode write value reset clock 32 1s yes 000 yes no yes yes yes data register read no as is no no no yes no
ad7730/ad7730l C24C rev. a analog input analog input channels the ad7730 contains two differential analog input channels, a primary input channel, ain1, and a secondary input channel, ain2. the input pairs provide programmable gain, differential channels which can handle either unipolar or bipolar input signals. it should be noted that the bipolar input signals are referenced to the respective ain(C) input of the input pair. the secondary input channel can also be reconfigured as two digital output port bits. a two-channel differential multiplexer switches one of the two input channels to the on-chip buffer amplifier. this multiplexer is controlled by the ch0 and ch1 bits of the mode register. when the analog input channel is switched, the rdy output goes high and the settling time of the part must elapse before a valid word from the new channel is available in the data regis- ter (indicated by rdy going low). buffered inputs the output of the multiplexer feeds into a high impedance input stage of the buffer amplifier. as a result, the analog inputs can handle significant source impedances. this buffer amplifier has an input bias current of 50 na (chp = 1) and 60 na (chp = 0). this current flows in each leg of the analog input pair. the offset current on the part is the difference between the input bias on the legs of the input pair. this offset current is less than 10 na (chp = 1) and 30 na (chp = 0). large source resis- tances result in a dc offset voltage developed across the source resistance on each leg, but matched impedances on the analog input legs will reduce the offset voltage to that generated by the input offset current. analog input ranges the absolute input voltage range is restricted to between agnd + 1.2 v to av dd C 0.95 v, which also places restrictions on the common-mode range. care must be taken in setting up the common-mode voltage and input voltage range so these limits are not exceeded, otherwise there will be a degradation in linearity performance. in some applications, the analog input range may be biased either around system ground or slightly below system ground. in such cases, the agnd of the ad7730 must be biased negative with respect to system ground so the analog input voltage does not go within 1.2 v of agnd. care should taken to ensure that the differential between either av dd or dv dd and this biased agnd does not exceed 5.5 v. this is discussed in more detail in the applications section. programmable gain amplifier the output from the buffer amplifier is summed with the output of the 6-bit offset dac before it is applied to the input of the on-chip programmable gain amplifier (pga). the pga can handle four different unipolar input ranges and four bipolar ranges. with the hiref bit of the mode register at 0 and a +2.5 v reference (or the hiref bit at 1 and a +5 v reference), the unipolar ranges are 0 mv to +10 mv, 0 mv to +20 mv, 0 mv to +40 mv, and 0 mv to +80 mv, while the bipolar ranges are 10 mv, 20 mv, 40 mv and 80 mv. these are the nominal ranges that should appear at the input to the on-chip pga. offset dac the purpose of the offset dac is to either add or subtract an offset so the input range at the input to the pga is as close as possible to the nominal. if the output of the 6-bit offset dac is 0 v, the differential voltage ranges that appear at the analog input to the part will also appear at the input to the pga. if, however, the offset dac has an output voltage other than 0 v, the input range to the analog inputs will differ from that applied to the input of the pga. the offset dac has five magnitude bits and one sign bit. the sign bit determines whether the value loaded to the five magni- tude bits is added to or subtracted from the voltage at the ana- log input pins. control of the offset dac is via the dac register which is discussed previously in the on-chip registers section. with a 5 v reference applied between the ref in pins, the resolution of the offset dac is 2.5 mv with a range that allows addition or subtraction of 77.5 mv. with a 2.5 v refer- ence applied between the ref in pins, the resolution of the offset dac is 1.25 mv with a range that allows addition or subtraction of 38.75 mv. following is an example of how the offset dac works. if the differential input voltage range the user had at the analog input pins was +20 mv to +30 mv, the offset dac should be pro- grammed to subtract 20 mv of offset so the input range to the pga is 0 mv to +10 mv. if the differential input voltage range the user had at the analog input pins was C60 mv to +20 mv, the offset dac should be programmed to add 20 mv of offset so the input range to the pga is 40 mv. bipolar/unipolar inputs the analog inputs on the ad7730 can accept either unipolar or bipolar input voltage ranges. bipolar input ranges do not imply that the part can handle negative voltages with respect to system ground on its analog inputs unless the agnd of the part is also biased below system ground. unipolar and bipolar signals on the ain(+) input are referenced to the voltage on the respective ain(C) input. for example, if ain(C) is +2.5 v and the ad7730 is configured for an analog input range of 0 to +10 mv w ith no dac offset correction, the input voltage range on the ain(+) input is +2.5 v to +2.51 v. similarly, if ain(C) is +2.5 v and the ad7730 is configured for an analog input range of 80 mv with no dac offset correction, the analog input range on the ain(+) input is +2.42 v to +2.58 v (i.e., 2.5 v 80 mv). bipolar or unipolar options are chosen by programming the b /u bit of the mode register. this programs the selected channel for either unipolar or bipolar operation. programming the chan- nel for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. when the ad7730 is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000 and a full- scale input voltage resulting in a code of 111 . . . 111. when the ad7730 is configured for bipolar operation, the coding is offset binary with a negative full scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000 and a positive full scale voltage resulting in a code of 111 . . . 111.
ad7730/ad7730l rev. a C25C burnout currents the ad7730 contains two 100 na constant current generators, one source current from av dd to ain(+) and one sink current from ain(C) to agnd. the currents are switched to the se- lected analog input pair. both currents are either on or off, depending on the bo bit of the mode register. these currents can be used in checking that a transducer is still operational before attempting to take measurements on that channel. if the currents are turned on, allowed flow in the transducer, a mea- surement of the input voltage on the analog input taken and the voltage measured is full scale, it indicates that the transducer has gone open-circuit. if the voltage measured is 0 v, it indicates that the transducer has gone short circuit. for normal operation, these burnout currents are turned off by writing a 0 to the bo bit. the current sources work over the normal absolute input voltage range specifications. reference input the ad7730s reference inputs, ref in(+) and ref in(C), provide a differential reference input capability. the common- mode range for these differential inputs is from agnd to av dd . the nominal reference voltage, v ref (ref in(+) ref in(C)), for specified operation is +2.5 v with the hiref bit at 0 v and +5 v with the hiref bit at 1. the part is also functional with v ref of +2.5 v with the hiref bit at 1. this results in a halving of all input ranges. the resolution in nv will be unaltered but will appear halved in terms of counts. both reference inputs provide a high impedance, dynamic load. the typical average dc i nput leakage current over temperature is 8.5 m a with hiref = 1 and v ref = +5 v, and 2.5 m a with hiref = 0 and v ref = +2.5 v. because the input impedance of each reference input is dynamic, external resistance/capacitance combinations on these inputs may result in gain errors on the part. the ad7730 can be operated in either ac or dc mode. if the bridge excitation is fixed dc, the ad7730 should be operated in dc mode. if the analog input and the reference inputs are externally chopped before being applied to the part the ad7730 should be operated in ac mode and not dc mode. in ac mode, it is assumed that both the analog inputs and reference inputs are chopped and as a result change phase every alternate chopping cycle. if the chopping is synchronized by the ad7730 (using the acx signals to control the chopping) the part then takes into account the reversal of the analog input and reference input signals. the output noise performance outlined in tables i through iv is for an analog input of 0 v and is unaffected by noise on the reference. to obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the ad7730. if the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the ad7730. in applications where the excitation voltage for the bridge transducer on the analog input also drives the refer- ence v oltage for the part, the effect of the noise in the excita- tion voltage will be removed as the application is ratiometric. figure 7 shows how the reference voltage can be connected in a ratiometric fashion in a dc-excited bridge application. in this case, the excitation voltage for the ad7730 and the transducer is a dc voltage. the hiref bit of the mode register should be set to 1. figure 8 meanwhile shows how the reference can be connected in a ratiometric fashion in an ac-excited bridge av dd dv dd agnd dgnd ad7730 excitation voltage = +5v in+ outC inC out+ ref in(+) ref in(C) ain1(+) ain1(C) figure 7. ratiometric generation of reference in dc- excited bridge application av dd dv dd excitation voltage = +5v agnd dgnd in+ outC inC out+ ad7730 ref in(+) ref in(C) ain1(+) ain1(C) acx acx ac excitation clock figure 8. ratiometric generation of reference in ac- excited bridge application application. in this case, both the reference voltage for the part and the excitation voltage for the transducer are chopped. once again, the hiref bit should be set to 1. if the ad7730 is not used in a ratiometric application, a low noise reference should be used. recommended 2.5 v reference voltage sources for the ad7730 include the ad780, ref43 and ref192. if any of these references are used as the reference source for the ad7730, the hiref bit should be set to 0. it is generally recommended to decouple the output of these references to further reduce the noise level. reference detect the ad7730 includes on-chip circuitry to detect if the part has a valid reference for conversions or calibrations. if the volt- age between the ref in(+) and ref in(C) pins goes below 0.3 v or either the ref in(+) or ref in(C) inputs is open circuit, the ad7730 detects that it no longer has a valid reference. in this case, the no ref bit of the status register is set to a 1. if the ad7730 is performing normal conversions and the no ref bit becomes active, the part places all ones in the data register. therefore, it is not necessary to continuously monitor the status of the no ref bit when performing conversions. it is only necessary to verify its status if the conversion result read from the data register is all 1s.
ad7730/ad7730l C26C rev. a if the ad7730 is performing either an offset or gain calibration and the noref bit becomes active, the updating of the respec- tive calibration register is inhibited to avoid loading incorrect coefficients to this register. if the user is concerned about verify- ing that a valid reference is in place every time a calibration is performed, then the status of the noref bit should be checked at the end of the calibration cycle. sigma-delta modulator a sigma-delta adc generally consists of two main blocks, an analog modulator and a digital filter. in the case of the ad7730, the analog modulator consists of a difference amplifier, an inte- grator block, a comparator and a feedback dac as illustrated in figure 9. in operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback dac. the difference between these two signals is integrated and fed to the comparator. the output of the comparator provides the input to the feedback dac so that the system functions as a negative feedback loop that tries to minimize the difference signal. the digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. this duty cycle data can be recovered as a data word using the digital filter. the sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. the integrator in the modulator shapes the quantization noise (which results from the analog-to-digital conversion) so that the noise is pushed toward one half of the modulator frequency. the digital filter then bandlimits the re- sponse to a frequency significantly lower than one half of the modulator frequency. in this manner, the 1-bit output of the comparator is translated into a bandlimited, low noise output from the ad7730. dac integrator analog input difference amp comparator digital filter digital data figure 9. sigma-delta modulator block diagram digital filtering filter architecture the output of the modulator feeds directly into the digital filter. this digital filter consists of two portions, a first stage filter and a second stage filter. the first stage filter is a sinc 3 , low-pass filter. the cutoff frequency and output rate of this first stage filter is programmable. the second stage filter has three distinct modes of operation. in its normal mode, it provides a low-pass fir filter that processes the output of the first stage filter. when a step change is detected on the analog input, this second stage filter enters a second mode where it performs a variable number of averages for some time after the step change and then the second stage filter switches back to the fir filter. the third option for the second stage filter is that it is completely bypassed so the only filtering provided on the ad7730 is the first stage. the various filter stages and options are discussed in the follow- ing sections. first stage filter the first stage filter is a low-pass, sinc 3 or (sinx/x) 3 filter whose primary function is to remove the quantization noise introduced at the modulator. the cutoff frequency and output rate of this filter is programmed via the sf0 to sf11 bits of the filter reg- ister. the frequency response for this first stage filter is shown in figure 10. the response of this first stage filter is similar to that of an averaging filter but with a sharper roll-off. the output rate for the filter corresponds with the positioning of the first notch of the filters frequency response. thus, for the plot of figure 10, where the output rate is 600 hz (f clk in = 4.9152 mhz and sf = 512), the first notch of the filter is at 600 hz. the notches of this sinc 3 filter are repeated at multiples of the first notch. the filter provides attenuation of better than 100 db at these notches. programming a different cutoff frequency via sf0 C sf11 does not alter the profile of the filter response; it changes the fre- quency of the notches as outlined in the filter registers section. this response is repeated at either side of the input sampling frequency (307 khz) and at either side of multiples of the input sampling frequency. frequency C hz 0 C60 C100 0 1800 gain C db 200 400 600 800 1000 1200 1400 1600 C10 C50 C70 C90 C30 C40 C80 C20 C120 C110 figure 10. frequency response of first stage filter the first stage filter has two basic modes of operation. the primary mode of operation for weigh-scale applications is chop mode, which is achieved by placing a 1 in the chp bit of the filter register. the part should be operated in this mode when drift and noise rejection are important criteria in the application. the alternative mode of operation is the nonchop mode, with chp at 0, which would be used when higher throughput rates are a concern or in applications where the reduced rejection at the chopping frequency in chop mode is an issue. nonchop mode with chop mode disabled on the ad7730, the first stage filter continuously processes input data and produces a result at an output rate determined by the sf word. operating in nonchop mode can result in a 20% reduction in noise for a given band- width, but without the excellent drift and noise rejection ben- efits which accrue from chopping the part. the output update and first notch of this first stage filter correspond and are deter- mined by the relationship: output rate = f clk in 16 1 sf where sf is the decimal equivalent of the data loaded to the sf bits of the filter register and f clk in is the master clock frequency.
ad7730/ad7730l rev. a C27C chop mode with chop mode enabled on the ad7730, the signal processing chain is synchronously chopped at the analog input and at the output of the first stage filter. this means that for each output of the first stage filter to be computed, the full settling time of the filter has to elapse. this results in an output rate from the filter that is three times lower than for a given sf word than for nonchop mode. the output update and first notch of this first stage filter correspond and are determined by the relationship: output rate = f clk in 16 1 3 sf where sf is the decimal equivalent of the data loaded to the sf bits of the filter register and f clk in is the master clock frequency. second stage filter as stated earlier, the second stage filter has three distinct modes of operation which result in a different overall filter profile for the part. the modes of operation of the second stage filter are discussed in the following sections along with the different filter profiles which result. normal fir operation the normal mode of operation of the second stage filter is as a 22-tap low-pass fir filter. this second stage filter processes the output of the first stage filter and the net frequency response of the filter is simply a product of the filter response of both filters. the overall filter response of the ad7730 is guaranteed to have no overshoot. figure 11 shows the full frequency response of the ad7730 when the second stage filter is set for normal fir operation. this response is for chop mode enabled with the decimal equivalent of the word in the sf bits set to 512 and a master clock frequency of 4.9152 mhz. the response will scale proportionately with master clock frequency. the response is shown from dc to 100 hz. the rejection at 50 hz 1 hz and 60 hz 1 hz is better than 88 db. the C3 db frequency for the frequency response of the ad7730 with the second stage filter set for normal fir operation and chop mode enabled is determined by the following relationship: f 3 db = 0.0395 f clk in 16 1 3 sf in this case, f 3 db = 7.9 hz and the stopband, where the attenua- tion is greater than 64.5 db, is determined by: f stop = 0.14 f clk in 16 1 3 sf in this case, f stop = 28 hz. frequency C hz 0 C60 C100 090 gain C db 10 20 30 40 50 60 70 80 C10 C50 C70 C90 C30 C40 C80 C20 C120 C110 100 figure 11. detailed full frequency response of ad7730 (second stage filter as normal fir, chop enabled) figure 12 shows the frequency response for the same set of conditions as for figure 11, but in this case the response is shown out to 600 hz. this response shows that the attenuation of input frequencies close to 200 hz and 400 hz is significantly less than at other input frequencies. these peaks in the fre- quency response are a by-product of the chopping of the input. the plot of figure 12 is the amplitude for different input fre- quencies. note that because the output rate is 200 hz for the conditions under which figure 12 is plotted, if something ex- isted in the input frequency domain at 200 hz, it would be aliased and appear in the output frequency domain at dc. frequency C hz 0 C60 C100 0 450 gain C db 50 100 150 200 250 300 350 400 C10 C50 C70 C90 C30 C40 C80 C20 C120 C110 500 550 600 figure 12. expanded full frequency response of ad7730 (second stage filter as normal fir, chop enabled)
ad7730/ad7730l C28C rev. a because of this effect, care should be taken in choosing an out- put rate that is close to the line frequency in the application. if the line frequency is 50 hz, an output update rate of 50 hz should not be chosen as it will significantly reduce the ad7730s line frequency rejection (the 50 hz will appear as a dc effect with only 6 db attenuation). choosing an output rate of 55 hz will result in a 6 dbattenuated aliased frequency of 5 hz with only a further 25 db attenuation based on the filter profile. this number is based on the filter roll-off and figure 11 can be used as a reference by dividing the frequency scale by a factor of 4. choosing 57 hz as the output rate will give better than 90 db atten uation of the aliased line frequency which appears as a 7 hz signal. similarly, multiples of the line frequency should be avoided as the output rate because harmonics of the line fre- quency will not be fully attenuated. the programmability of the ad7730s output rate should allow the user to readily choose an output rate that overcomes this issue. an alternative is to use the part in nonchop mode. figure 13 shows the frequency response for the ad7730 with the second stage filter set for normal fir operation, chop mode disabled, the decimal equivalent of the word in the sf bits set to 1536 and a master clock frequency of 4.9152 mhz. the response is analogous to that of figure 11, with the three-times-larger sf word producing the same 200 hz output rate. once again, the response will scale proportionally with master clock frequency. the response is shown from dc to 100 hz. the rejection at 50 hz 1 hz, and 60 hz 1 hz is better than 88 db. frequency C hz 0 C60 C100 090 gain C db 10 20 30 40 50 60 70 80 C10 C50 C70 C90 C30 C40 C80 C20 C120 C110 100 figure 13. detailed full frequency response of ad7730 (second stage filter as normal fir, chop disabled) the C3 db frequency for the frequency response of the ad7730 with the second stage filter set for normal fir operation and chop mode enabled, is determined by the following relationship: f 3 db = 0.039 f clk in 16 1 sf in this case, f 3 db = 7.8 hz and the stop band, where the attentua- tion is greater than 64.5 db, is determined by: f stop = 0.14 f clk in 16 1 sf in this case, f 3 db = 28 hz. figure 14 shows the frequency response for the same set of conditions as for figure 13, but in this case the response is shown out to 600 hz. this plot is comparable to that of figure 12. the most notable difference is the absence of the peaks in the response at 200 hz and 400 hz. as a result, interference at these frequencies will be effectively eliminated before being aliased back to dc. frequency C hz 0 C60 C100 0 450 gain C db 50 100 150 200 250 300 350 400 C10 C50 C70 C90 C30 C40 C80 C20 C120 C110 500 550 600 figure 14. expanded full frequency response of ad7730 (second stage filter as normal fir, chop disabled)
ad7730/ad7730l rev. a C29C faststep mode the second mode of operation of the second stage filter is in fast step mode which enables it to respond rapidly to step inputs. this fast step mode is enabled by placing a 1 in the fast bit of the filter register. if the fast bit is 0, the part continues to process step inputs with the normal fir filter as the second stage filter. with fast step mode enabled, the second stage filter will continue to process steady state inputs with the filter in its normal fir mode of operation. however, the part is continuously monitoring the output of the first stage filter and comparing it with the second previous output. if the difference between these two outputs is greater than a predeter- mined threshold (1% of full scale), the second stage filter switches to a simple moving average computation. when the step change is detected, the stdy bit of the status register goes to 1 and will not return to 0 until the fir filter is back in the processing loop. the initial number of averages in the moving average computa- tion is either 2 (chop enabled) or 1 (chop disabled). the num- ber of averages will be held at this value as long as the threshold is exceeded. once the threshold is no longer exceeded (the step on the analog input has settled), the number of outputs used to compute the moving average output is increased. the first and second outputs from the first stage filter where the threshold is no longer exceeded is computed as an average by two, then four outputs with an average of four, eight outputs with an average of eight, and six outputs with an average of 16. at this time, the second stage filter reverts back to its normal fir mode of opera- tion. when the second stage filter reverts back to the normal fir, the stdy bit of the status register goes to 0. figure 15 shows the different responses to a step input with fast step mode enabled and disabled. the vertical axis shows the code value returned by the ad7730 and indicates the set- tling of the output to the input step change. the horizontal axis shows the number of outputs it takes for that settling to occur. the positive input step change occurs at the fifth output. in fast step mode, the output has settled to the final value by the eighth output. in normal mode, the output has not reached close to its final value until after the 25th output. number of outputs 20000000 15000000 0 025 5 code 10 15 20 10000000 5000000 figure 15. step response for fast step and normal operation in fast step mode, the part has settled to the new value much faster. with chopping enabled, the fast step mode settles to its value in two outputs, while the normal mode settling takes 23 outputs. between the second and 23rd output, the fast step mode produces a settled result, but with additional noise com- pared to the specified noise level for its operating conditions. it starts at a noise level that is comparable to skip mode and as the averaging increases ends up at the specified noise level. the complete settling time to where the part is back within the specified noise number is the same for fast step mode and normal mode. as can be seen from figure 13, the fast step mode gives a much earlier indication of where the output chan- nel is going and its new value. this feature is very useful in weighing applications to give a much earlier indication of the weight, or in an application scanning multiple channels where the user does not have to wait the full settling time to see if a channel has changed value. skip mode the final method for operating the second stage filter is where it is bypassed completely. this is achieved by placing a 1 in the skip bit of the filter register. when skip mode is enabled, it means that the only filtering on the part is the first stage, sinc 3 , filter. as a result, the complete filter profile is as described ear- lier for the first stage filter and illustrated in figure 10. in skip mode, because there is much less processing of the data to derive each individual output, the normal mode settling time for the part is shorter. as a consequence of the lesser filtering, however, the output noise from the part will be significantly higher for a given sf word. for example with a 20 mv, an sf word of 1536 and chp = 0, the output rms noise increases from 80 nv to 200 nv. with a 10 mv input range, an sf word of 1024 and chp = 1, the output rms noise goes from 60 nv to 200 nv. with chopping disabled and skip mode enabled, each output from the ad7730 is a valid result in itself. however, with chop- ping enabled and skip mode enabled, the outputs from the ad7730 must be handled in pairs as each successive output is from reverse chopping polarities. calibration the ad7730 provides a number of calibration options which can be programmed via the md2, md1 and md0 bits of the mode register. the different calibration options are outlined in the mode register and calibration operations sections. a cali- bration cycle may be initiated at any time by writing to these bits of the mode register. calibration on the ad7730 removes offset and gain errors from the device. the ad7730 gives the user access to the on-chip calibration registers allowing the microprocessor to read the devices cali- bration coefficients and also to write its own calibration coeffi- cients to the part from prestored values in e 2 prom. this gives the microprocessor much greater control over the ad7730s calibration procedure. it also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in e 2 prom. the values in these calibration registers are 24 bits wide. in addition, the span and offset for the part can be adjusted by the user.
ad7730/ad7730l C30C rev. a internally in the ad7730, the coefficients are normalized before being used to scale the words coming out of the digital filter. the offset calibration register contains a value which, when normalized, is subtracted from all conversion results. the gain calibration register contains a value which, when normalized, is multiplied by all conversion results. the offset calibration coeffi- cient is subtracted from the result prior to the multiplication by the gain coefficient. the ad7730 offers self-calibration or system calibration facili- ties. for full calibration to occur on the selected channel, the on- chip microcontroller must record the modulator output for two different input conditions. these are zero-scale and full- scale points. these points are derived by performing a conver- sion on the different input voltages provided to the input of the modulator during calibration. the result of the zero-scale calibration conversion is stored in the offset calibration regis- ter for the appropriate channel. the result of the full-scale calibration conversion is stored in the gain calibration register for the appropriate channel. with these readings, the microcon- troller can calculate the offset and the gain slope for the input to output transfer function of the converter. internally, the part works with 33 bits of resolution to determine its conversion result of either 16 bits or 24 bits. the sequence in which the zero-scale and full-scale calibration occurs depends upon the type of full-scale calibration being performed. the internal full-scale calibration is a two-step cali- bration that alters the value of the offset calibration register. thus, the user must perform a zero-scale calibration (either inte rnal or system) after an internal full-scale calibration to correct the offset calibration register contents. when using system full-scale calibration, it is recommended that the zero-scale calibration (either internal or system) is performed first. since the calibration coefficients are derived by performing a conversion on the input voltage provided, the accuracy of the calibration can only be as good as the noise level the part pro- vides in normal mode. to optimize the calibration accuracy, it is recommended to calibrate the part at its lowest output rate where the noise level is lowest. the coefficients generated at any output update rate will be valid for all selected output update rates. this scheme of calibrating at the lowest output update rate does mean that the duration of calibration is longer. internal zero-scale calibration an internal zero-scale calibration is initiated on the ad7730 by writing the appropriate values (1, 0, 0) to the md2, md1 and md0 bits of the mode register. in this calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (i.e., ain(+) = ain(C) = externally-applied ain(C) voltage). the pga is set for the selected gain (as per the rn1, rn0 bits in the mode register) for this internal zero-scale calibration conversion. the calibration is performed with dc excitation regardless of the status of the ac bit. the duration time of the calibration de- pends upon the chp bit of the filter register. with chp = 1, the duration is 22 1/output rate; with chp = 0, the duration is 24 1/output rate. at this time the md2, md1 and md0 bits in the mode register return to 0, 0, 0 (sync or idle mode for the ad7730). the rdy line goes high when calibration is initiated and returns low when calibration is complete. note that the part has not performed a conversion at this time; it has simply performed a zero-scale calibration and updated the off- set calibration register for the selected channel. the user must write either 0, 0, 1 or 0, 1, 0 to the md2, md1, md0 bits of the mode register to initiate a conversion. if rdy is low before (or goes low during) the calibration command write to the mode register, it may take up to one modulator cycle (mclk in/32) before rdy goes high to indicate that calibration is in progress. therefore, rdy should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register. for bipolar input ranges in the internal zero-scale calibrating mode, the sequence is very similar to that just outlined. in this case, the zero-scale point is exactly the same as above but since the part is configured for bipolar operation, the output code for zero differential input is 800000 hex in 24-bit mode. the internal zero-scale calibration needs to be performed as one part of a two part full calibration. however, once a full calibration has been performed, additional internal zero-scale calibrat ions can be performed by themselves to adjust the parts zero-scale point only. when performing a two step full calibration care should be taken as to the sequence in which the two steps are performed. if the internal zero-scale calibration is one part of a full self-calibration, then it should take place after an internal full-scale calibration. if it takes place in association with a system full-scale calibration, then this internal zero-scale calibration should be performed first. internal full-scale calibration an internal full-scale calibration is initiated on the ad7730 by writing the appropriate values (1, 0, 1) to the md2, md1 and md0 bits of the mode register. in this calibration mode, the full-scale point used in determining the calibration coefficients is with an internally-generated full-scale voltage. this full-scale voltage is derived from the reference voltage for the ad7730 and the pga is set for the selected gain (as per the rn1, rn0 bits in the mode register) for this internal full-scale calibration conversion. in order to meet the post-calibration numbers quoted in the specifications, it is recommended that internal full-scale calibra- tions be performed on the 80 mv range. this applies even if the subsequent operating mode is on the 10 mv, 20 mv or 40 mv input ranges. the internal full-scale calibration is a two-step sequence that runs when an internal full-scale calibration command is written to the ad7730. one part of the calibration is a zero-scale cali- bration and as a result, the contents of the offset calibration register are altered during this internal full-scale calibration. the user must therefore perform a zero-scale calibration (either internal or system) after the internal full-scale calibration. this zero-scale calibration should be performed at the operating input range. this means that internal full-scale calibrations cannot be performed in isolation. the calibration is performed with dc excitation regardless of the status of the ac bit. the duration time of the calibration de- pends upon the chp bit of the filter register. with chp = 1, the duration is 44 1/output rate; with chp = 0, the duration is 48 1/output rate. at this time the md2, md1 and md0 bits in the mode register return to 0, 0, 0 (sync or idle mode for the ad7730). the rdy line goes high when calibration is initiated and returns low when calibration is complete. note that the part has not performed a conversion at this time. the
ad7730/ad7730l rev. a C31C user must write either 0, 0, 1 or 0, 1, 0 to the md2, md1, md0 b its of the mode register to initiate a conversion. if rdy is low before (or goes low during) the calibration com- mand write to the mode register, it may take up to one modulator cycle (mclk in/32) before rdy goes high to indicate that calibration is in progress. therefore, rdy should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register. system zero-scale calibration system calibration allows the ad7730 to compensate for system gain and offset errors as well as its own internal errors. system calibration performs the same slope factor calculations as self- calibration, but uses voltage values presented by the system to the ain inputs for the zero- and full-scale points. a system zero-scale calibration is initiated on the ad7730 by writing the appropriate values (1, 1, 0) to the md2, md1 and md0 bits of the mode register. in this calibration mode, with a unipolar input range, the zero-scale point used in determin- ing the calibration coefficients is the bottom end of the trans- fer function. the systems zero-scale point is applied to the ad7730s ain input before the calibration step and this voltage must remain stable for the duration of the system zero-scale calibration. the pga is set for the selected gain (as per the rn1, rn0 bits in the mode register) for this system zero-scale calibration conversion. the allowable range for the system zero- scale voltage is discussed in the span and offsets section. the calibration is performed with either ac or dc excitation, depending on the status of the ac bit. the duration time of the calibration depends upon the chp bit of the filter register. with chp = 1, the duration is 22 1/output rate; with chp = 0, the duration is 24 1/output rate. at this time the md2, md1 and md0 bits in the mode register return to 0, 0, 0 (sync or idle mode for the ad7730). the rdy line goes high when calibration is initiated and returns low when calibration is complete. note that the part has not performed a conversion at this time; it has simply performed a zero-scale calibration and updated the offset calibration register for the selected channel. the user must write either 0, 0, 1 or 0, 1, 0 to the md2, md1, md0 bits of the mode register to initiate a conversion. if rdy is low before (or goes low during) the cali- bration command write to the mode register, it may take up to one modulator cycle (mclk in/32) b efore rdy goes high to indicate that calibration is in progress. therefore, rdy should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register. for bipolar input ranges in the system zero-scale calibrating mode, the sequence is very similar to that just outlined. in this case, the zero-scale point is the midpoint of the ad7730s transfer function. the system zero-scale calibration needs to be performed as one part of a two part full calibration. however, once a full calibra- tion has been performed, additional system zero-scale calibra- tions can be performed by themselves to adjust the parts zero-scale point only. when performing a two-step full calibra- tion care should be taken as to the sequence in which the two steps are performed. if the system zero-scale calibration is one part of a full system calibration, then it should take place before a system full-scale calibration. if it takes place in association with an internal full-scale calibration, then this system zero-scale calibration should be performed after the full-scale calibration. system full-scale calibration a system full-scale calibration is initiated on the ad7730 by writing the appropriate values (1, 1, 1) to the md2, md1 and md0 bits of the mode register. system full-scale calibration is performed using the system's positive full-scale voltage. this full-scale voltage must be set up before the calibration is initi- ated, and it must remain stable throughout the calibration step. the system full-scale calibration is performed at the selected gain (as per the rn1, rn0 bits in the mode register). the calibration is performed with either ac or dc excitation, depending on the status of the ac bit. the duration time of the calibration depends upon the chp bit of the filter register. with chp = 1, the duration is 22 1/output rate; with chp = 0, the duration is 24 1/output rate. at this time the md2, md1 and md0 bits in the mode register return to 0, 0, 0 (sync or idle mode for the ad7730). the rdy line goes high when calibration is initiated, and returns low when calibration is complete. note that the part has not performed a conversion at this time; it has simply performed a full-scale calibration and updated the gain calibration register for the selected channel. the user must write either 0, 0, 1 or 0, 1, 0 to the md2, md1, md0 bits of the mode register to initiate a conversion. if rdy is low before (or goes low during) the calibration command write to the mode register, it may take up to one modulator cycle (mclk in/32) before rdy goes high to indicate that calibration is in progress. therefore, rdy should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register. the system full-scale calibration needs to be performed as one part of a two part full calibration. once a full calibration has been performed, however, additional system full-scale calibra- tions can be performed by themselves to adjust the part's gain calibration point only. when performing a two-step full calibra- tion care should be taken as to the sequence in which the two steps are performed. a system full-scale calibration should not be carried out unless the part contains valid zero-scale coeffi- cients. therefore, an internal zero-scale calibration or a system zero-scale calibration must be performed before the system full- scale calibration when a full two-step calibration operation is being performed. span and offset limits whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. the overriding requirement in determining the amount of offset and gain which can be accommodated by the part is the require- ment that the positive full-scale calibration limit is 1.05 fs, where fs is 10 mv, 20 mv, 40 mv or 80 mv depending on the rn1, rn0 bits in the mode register. this allows the input range to go 5% above the nominal range. the built-in head- room in the ad7730s analog modulator ensures that the part will still operate correctly with a positive full-scale voltage that is 5% beyond the nominal.
ad7730/ad7730l C32C rev. a the range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 fs and a maximum value of 2.1 fs. however, the span (which is the difference between the bottom of the ad7730s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. the amount of offset which can be accommo- dated depends on whether the unipolar or bipolar mode is being used. once again, the offset has to take into account the limita- tion on the positive full-scale voltage. in unipolar mode, there is considerable flexibility in handling negative (with respect to ain(C)) offsets. in both unipolar and bipolar modes, the range of positive offsets that can be handled by the part depends on the selected span. therefore, in determining the limits for sys- tem zero-scale and full-scale calibrations, the user has to ensure that the offset range plus the span range does exceed 1.05 fs. this is best illustrated by looking at a few examples. if the part is used in unipolar mode with a required span of 0.8 fs, the offset range the system calibration can handle is from C1.05 fs to +0.25 fs. if the part is used in unipolar mode with a required span of fs, the offset range the system cali- bration can handle is from C1.05 fs to +0.05 fs. simi larly, if the part is used in unipolar mode and required to remove an offset of 0.2 fs, the span range the system calibration can handle is 0.85 fs. if the part is used in bipolar mode with a required span of 0.4 fs, the offset range the system calibration can handle is from C0.65 fs to +0.65 fs. if the part is used in bipolar mode with a required span of fs, the offset range the system calibration can handle is from C0.05 fs to +0.05 fs. simi- larly, if the part is used in bipolar mode and required to remove an offset of 0.2 fs, the span range the system calibration can handle is 0.85 fs. figure 16 summarizes the span and offset ranges. upper limit. ad7730s input voltage cannot exceed this 0v differential 1.05 3 fs. nominal zero-scale point C1.05 3 fs. lower limit. ad7730s input voltage cannot exceed this ad7730 input range (0.8 3 fs to 2.1 3 fs) gain calibrations expand or contract the ad7730s input range zero-scale calibrations move input range up or down figure 16. span and offset limits power-up and calibration on power-up, the ad7730 performs an internal reset which sets the contents of the internal registers to a known state. there are default values loaded to all registers after a power-on or reset. the default values contain nominal calibration coefficients for the calibration registers. to ensure correct calibration for the device, a calibration routine should be performed after power-up. the power dissipation and temperature drift of the ad7730 are low and no warm-up time is required before the initial calibra- tion is performed. if, however, an external reference is being used, this reference must have stabilized before calibration is initiated. similarly, if the clock source for the part is generated from a crystal or resonator across the mclk pins, the start-up time for the oscillator circuit should elapse before a calibration is initiated on the part (see below). drift considerations the ad7730 uses chopper stabilization techniques to minimize input offset drift. charge injection in the analog multiplexer and dc leakage currents at the analog input are the primary sources of offset voltage drift in the part. the dc input leakage current is essentially independent of the selected gain. gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. it is not affected by leakage currents. when operating the part in chop mode (chp = 1), the signal chain including the first-stage filter is chopped. this chopping reduces the overall offset drift to 5 nv/ c. integral and differen- tial linearity errors are not significantly affected by temperature changes. care must also be taken with external drift effects in order to achieve optimum drift performance. the user has to be espe- cially careful to avoid, as much as possible, thermocouple effects from junctions of different materials. devices should not be placed in sockets when evaluating temperature drift, there should be no links in series with the analog inputs and care must be taken as to how the input voltage is applied to the input pins. the true offset drift of the ad7730 itself can be evaluated by performing temperature drift testing of the part with the ain( C)/ain(C) input channel arrangement (i.e., internal shorted input, test mode). using the ad7730 clocking and oscillator circuit the ad7730 requires a master clock input, which may be an external cmos compatible clock signal applied to the mclk in pin with the mclk out pin left unconnected. alternatively, a crystal or ceramic resonator of the correct frequency can be connected between mclk in and mclk out in which case the clock circuit will function as an oscillator, providing the clock source for the part. the input sampling frequency, the modulator sampling frequency, the C3 db frequency, output update rate and calibration time are all directly related to the master clock frequency, f clk in . reducing the master clock frequency by a factor of two will halve the above frequencies and update rate and double the calibration time. the crystal or ceramic resonator is connected across the mclk in and mclk out pins, as per figure 17. capacitors c1 and c2 may or may not be required and may vary in value depend- ing on the crystal/resonator manufacturer's recommendations. the ad7730 has a capacitance of 5 pf on mclk in and 13 pf on mclk out so, in most cases, capacitors c1 and c2 will not be required to get the crystal/resonator operating at its cor- rect frequency.
ad7730/ad7730l rev. a C33C ad7730 crystal or ceramic resonator c1 c2 mclk in mclk out figure 17. crystal/resonator connections the on-chip oscillator circuit also has a start-up time associated with it before it has attained its correct frequency and correct voltage levels. the typical start-up time for the circuit is 6 ms, with a dv dd of +5 v and 8 ms with a dv dd of +3 v. the ad7730s master clock appears on the mclk out pin of the device. the maximum recommended load on this pin is one cmos load. when using a crystal or ceramic resonator to gen- erate the ad7730s clock, it may be desirable to then use this clock as the clock source for the system. in this case, it is recom- mended that the mclk out signal is buffered with a cmos buffer before being applied to the rest of the circuit. system synchronization the sync input allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part. this allows the user to start gathering samples of the ana- log input from a known point in time, i.e., the rising edge of sync . if multiple ad7730s are operated from a common master clock, they can be synchronized to update their output registers simul- taneously. a falling edge on the sync input resets the digital filter and analog modulator and places the ad7730 into a con- sistent, known state. while the sync input is low, the ad7730 will be maintained in this state. on the rising edge of sync , the modulator and filter are taken out of this reset state and on the next clock edge the part starts to gather input samples again. in a system using multiple ad7730s, a common signal to their sync inputs will synchronize their operation. this would nor- mally be done after each ad7730 has performed its own cali- bration or has had calibration coefficients loaded to it. the output updates will then be synchronized with the maximum possible difference between the output updates of the individual ad7730s being one mclk in cycle. single-shot conversions the sync input can also be used as a start convert command allowing the ad7730 to be operated in a conventional converter fashion. in this mode, the rising edge of sync starts conversion and the falling edge of rdy indicates when conversion is com- plete. the disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update. writing 0, 1, 0 to the md2, md1, md0 bits of the mode regis- ter has the same effect. this initiates a single conversion on the ad7730 with the part returning to idle mode at the end of conversion. once again, the full settling-time of the filter has to elapse before the data register is updated. reset input the reset input on the ad7730 resets all the logic, the digital filter and the analog modulator while all on-chip registers are reset to their default state. rdy is driven high and the ad7730 ignores all communications to any of its registers while the reset input is low. when the reset input returns high, the ad7730 starts to process data and rdy will return low after the filter has settled indicating a valid new word in the data register. however, the ad7730 operates with its default setup conditions after a reset and it is generally necessary to set up all registers and carry out a calibr ation after a reset command. the ad7730s on-chip oscillator circuit continues to function even when the reset input is low. the master clock signal continues to be available on the mclk out pin. therefore, in applications where the system clock is provided by the ad7730s clock, the ad7730 produces an uninterrupted master clock during reset commands. standby mode the standby input on the ad7730 allows the user to place the part in a power-down mode when it is not required to pro- vide conversion results. the part can also be placed in its standby mode by writing 0, 1, 1 to the md2, md1, md0 bits of the mode register. the ad7730 retains the contents of all its on-chip registers (including the data register) while in standby mode. data can still be read from the part in standby mode. the stby bit of the status register indicates whether the part is in standby or normal operating mode. when the standby pin is taken high, the part returns to operating as it had been prior to the standby pin going low. the standby input (or 0, 1, 1 in the md2, md1, md0 bits) does not affect the digital interface. it does, however, set the rdy bit and pin high and also sets the stdy bit high. when standby goes high again, rdy and stdy remain high until set low by a conversion or calibration. placing the part in standby mode, reduces the total current to 10 m a typical when the part is operated from an external master clock provided this master clock is stopped. if the external clock continues to run in standby mode, the standby current increases to 400 m a typical. if a crystal or ceramic resonator is used as the clock source, then the total current in standby mode is 400 m a typical. this is because the on-chip oscillator circuit continues to run when the part is in its standby mode. this is important in applications where the system clock is provided by the ad7730s clock, so that the ad7730 produces an uninterrupted master clock even when it is in its standby mode. digital outputs the ad7730 has two digital output pins, d0 and d1. when the den bit of the mode register is set to 1, these digital outputs assume the logic status of bits d0 and d1 of the mode register. it gives the user access to two digital port pins which can be programmed over the normal serial interface of the ad7730. the two outputs obtain their supply voltage from av dd , thus the outputs operate to 5 v levels even in cases where dv dd = +3 v.
ad7730/ad7730l C34C rev. a power supplies there is no specific power sequence required for the ad7730, either the av dd or the dv dd supply can come up first. while the latch-up performance of the ad7730 is very good, it is important that power is applied to the ad7730 before signals at ref in, ain or the logic input pins in order to avoid latch-up caused by excessive current. if this is not possible, the current that flows in any of these pins should be limited to less than 30 ma per pin and less than 100 ma cumulative. if separate sup- plies are used for the ad7730 and the system digital circuitry, the ad7730 should be powered up first. if it is not possible to guarantee this, current limiting resistors should be placed in series with the logic inputs to again limit the current to less than 30 ma per pin and less than 100 ma total. grounding and layout since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. the excellent common-mode rejection of the part will remove common-mode noise on these inputs. the analog and digital supplies to the ad7730 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter will provide rejection of broadband noise on the power supplies, except at integer mul- tiples of the modulator sampling frequency or multiples of the chop frequency in chop mode. the digital filter also removes noise from the analog and reference inputs provided those noise sources do not saturate the analog modulator. as a result, the ad7730 is more immune to noise interference than a conven- tional high resolution converter. however, because the resolu- tion of the ad7730 is so high and the noise levels from the ad7730 so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the ad7730 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad7730 is the only device requiring an agnd to dgnd connection, the ground planes should be connected at the agnd and dgnd pins of the ad7730. if the ad7730 is in a system where multiple devices require agnd to dgnd connections, the connection should still be made at one point only, a star ground point that should be established as closely as possible to the ad7730. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7730 to avoid noise coupling. the power supply lines to the ad7730 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is important when using high resolution adcs. all analog supplies should be decoupled with 10 m f tantalum in parallel with 0.1 m f ceramic capacitors to agnd. to achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. all logic chips should be decoupled with 0.1 m f disc ceramic capacitors to dgnd. in systems where a common supply voltage is used to drive both the av dd and dv dd of the ad7730, it is recommended that the systems av dd supply is used. this supply should have the recom- mended analog supply decoupling capacitors between the av dd pin of the ad7730 and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7730 and dgnd. evaluating the ad7730 performance a recommended layout for the ad7730 is outlined in the evalu- ation board for the ad7730. the evaluation board package includes a fully assembled and tested evaluation board, docu- mentation, software for controlling the board over the printer port of a pc and software for analyzing the ad7730s perfor- mance on the pc. the evaluation board order number is eval-ad7730eb. noise levels in the signals applied to the ad7730 may also affect performance of the part. the ad7730 allows two tech- niques for evaluating the true performance of the part, indepen- dent of the analog input signal. these schemes should be used after a calibration has been performed on the part. the first method is to select the ain1(C)/ain1(C) input chan- nel arrangement. in this case, the differential inputs to the ad7730 are internally shorted together to provide a zero differ- ential voltage for the analog modulator. external to the device, the ain1(C) input should be connected to a voltage which is within the allowable common-mode range of the part. the second scheme is to evaluate the part with a voltage near input full scale. this can be achieved by again using input pair ain1(C), but by adding a differential voltage via the tare dac. this allows the user to evaluate noise performance with a near full-scale voltage. the software in the evaluation board package allows the user to look at the noise performance in terms of counts, bits and nv. once the user has established that the noise performance of the part is satisfactory in this mode, an external input voltage can then be applied to the device incorporating more of the signal chain.
ad7730/ad7730l rev. a C35C serial interface the ad7730s programmable functions are controlled via a set of on-chip registers. access to these registers is via the parts serial interface. after power-on or reset , the device expects a write to its communications register. the data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. therefore, write access to one of the control registers on the part starts with a write opera- tion to the communications register followed by a write to the selected register. reading from the parts on-chip registers can take the form of either a single or continuous read. a single read from a register consists of a write to the communications regis- ter (with rw1 = 0 and rw0 = 1) followed by the read from the specified register. to perform continuous reads from a register, write to the communications register (with rw1 = 1 and rw0 = 0) to place the part in continuous read mode. the speci- fied register can then be read from continuously until a write operation to the communications register (with rw1 = 1 and rw0 = 1) which takes the part out of continuous read mode. when operating in continuous read mode, the part is continu- ously monitoring its din line. the din line should therefore be permanently low to allow the part to stay in continuous read mode. figure 5 and figure 6, shown previously, indicate the correct flow diagrams when reading and writing from the ad7730s registers. the ad7730s serial interface consists of five signals, cs , sclk, din, dout and rdy . the din line is used for transferring data into the on-chip registers while the dout line is used for accessing data from the on-chip registers. sclk is the serial clock input for the device and all data transfers (either on din or dout) take place with respect to this sclk signal. write operation the transfer of data into the part is to an input shift register. on completion of a write operation, data is transferred to the speci- fied register. this internal transfer will not take place until the correct number of bits for the specified register have been loaded to the input shift register. for example, the transfer of data from the input shift register takes place after eight serial clock cycles for a dac register write, while the transfer of data from the input shift register takes place after 24 serial clock cycles when writing to the filter register. figure 18 shows a timing diagram for a write operation to the input shift register of the ad7730. with the pol input at a logic high, the data is latched into the input shift register on the rising edge of sclk. with the pol input at a logic low, the data is latched into the input shift register on the falling edge of sclk. figure 18 also shows the cs input being used to decode the write operation to the ad7730. however, this cs input can be used in a number of different ways. it is possible to operate the part in three-wire mode where the cs input is tied low perma- nently. in this case, the sclk line should idle high between data transfer when the pol input is high and should idle low between data transfers when the pol input is low. for pol = 1, the first falling edge of sclk clocks data from the microcontrol- ler onto the din line of the ad7730. it is then clocked into the input shift register on the next rising edge of sclk. for pol = 0, the first clock edge that clocks data from the microcontroller onto the din line of the ad7730 is a rising edge. it is then clocked into the input shift register on the next falling edge of sclk. in other microcontroller applications which require a decoding of the ad7730, cs can be generated from a port line. in this case, cs would go low well in advance of the first falling edge of sclk (pol = 1) or the first rising edge of sclk (pol = 0). clocking of each bit of data is as just described. in dsp applications, the sclk is generally a continuous clock. in these applications, the cs input for the ad7730 is generated from a frame synchronization signal from the dsp. for proces- sors with the rising edge of sclk as the active edge, the pol input should be tied high. for processors with the falling edge of sclk as the active edge, the pol input should be tied low. in these applications, the first edge after cs goes low is the active edge. the msb of the data to be shifted into the ad7730 must be set up prior to this first active edge. read operation the reading of data from the part is from an output shift regis- ter. on initiation of a read operation, data is transferred from the specified register to the output shift register. this is a paral- lel shift and is transparent to the user. figure 19 shows a timing diagram for a read operation from the output shift register of the ad7730. with the pol input at a logic high, the data is clocked out of the output shift register on the falling edge of sclk. with the pol input at a logic low, the data is clocked out of the output shift register on the rising edge of sclk. figure 19 also shows the cs input being used to decode the read operation to the ad7730. however, this cs input can be used in a number of different ways. it is possible to operate the part in three-wire mode where the cs input is permanently tied low. in this case, the sclk line should idle high between data transfer when the pol input is high, and should idle low be- tween data transfers when the pol input is low. for pol = 1, the first falling edge of sclk clocks data from the output shift register onto the dout line of the ad7730. it is then clocked into the microcontroller on the next rising edge of sclk. for pol = 0, the first clock edge that clocks data from the ad7730 onto the dout line is a rising edge. it is then clocked into the microcontroller on the next falling edge of sclk. in other microcontroller applications which require a decoding of the ad7730, cs can be generated from a port line. in this case, cs would go low well in advance of the first falling edge of sclk (pol = 1) or the first rising edge of sclk (pol = 0). clocking of each bit of data is as just described.
ad7730/ad7730l C36C rev. a in dsp applications, the sclk is generally a continuous clock. in these applications, the cs input for the ad7730 is generated from a frame synchronization signal from the dsp. in these applications, the first edge after cs goes low is the active edge. the msb of the data to be shifted into the dsp must be set up prior to this first active edge. unlike microcontroller applica- tions, the dsp does not provide a clock edge to clock the msb from the ad7730. in this case, the cs of the ad7730 places the msb on the dout line. for processors with the rising edge of sclk as the active edge, the pol input should be tied high. in this case, the dsp takes data on the rising edge. if cs goes low while sclk is low, the msb is clocked out on the dout line from the cs . subsequent data bits are clocked from the falling edge of sclk. for processors with the falling edge of sclk as the active edge, the pol input should be tied low. in this case, the dsp takes data on the falling edge. if cs goes low while sclk is high, the msb is clocked out on the dout line from the cs . subsequent data bits are clocked from the rising edge of sclk. figure 18. read cycle timing diagram figure 19. write cycle timing diagram the rdy line is used as a status signal to indicate when data is ready to be read from the ad7730s data register. rdy goes low when a new data word is available in the data register. it is reset high when a read operation from the data register is com- plete. it also goes high prior to the updating of the data register to indicate when a read from the data register should not be initiated. this is to ensure that the transfer of data from the data register to the output shift register does not occur while the data register is being updated. it is possible to read the same data twice from the output register even though the rdy line returns high after the first read operation. care must be taken, however, to ensure that the read operations are not initiated as the next output update is about to take place. for systems with a single data line, the din and dout lines on the ad7730 can be connected together, but care must be taken in this case not to place the part in continuous read mode as the part monitors din while supplying data on dout and as a result, it may not be possible to take the part out of its continuous read mode. dout sclk (pol = 1) cs rdy msb t 5 t 7 t 9 lsb t 8 t 6 t 4 t 3 t 10 sclk (pol = 0) t 5a t 6 t 7 din sclk (pol = 1) cs msb t 12 t 15 lsb t 16 t 14 t 11 t 13 sclk (pol = 0) t 14 t 15
ad7730/ad7730l rev. a C37C configuring the ad7730 the ad7730 contains twelve on-chip registers that can be accessed via the serial interface. figure 5 and figure 6 have outlined a flowchart for the reading and writing of these registers. table xix and table xx outline sample pseudo-code for some commonly used routines. the required operating conditions will dictate the values loaded to the mode, filter and dac registers. the valu es given here are for example purposes only. table xix. pseudo-code for initiating a self-calibration after power-on/reset write 03 hex to serial port 1 /* writes to communications register setting next operation as write to filter register*/ write 800010 hex to serial port 1 /* writes to filter register setting a 50 hz output rate in chop mode*/ write 04 hex to serial port 1 /* writes to communications register setting next operation as write to dac register*/ write 23 hex to serial port 1 /* writes to dac register setting a subtraction value of 7.5 mv (5 v refer- ence) on the tare dac*/ write 02 hex to serial port /* writes to communications register setting next operation as write to mode register*/ write b180 hex to serial port /* writes to mode register initiating internal full-scale calibration for 0 mv to +10 mv input range*/ wait for rdy low /* wait for rdy pin to go low to indicate end of calibration cycle*/ write 02 hex to serial port /* writes to communications register setting next operation as write to mode register*/ write 9180 hex to serial port /* writes to mode register initiating internal zero-scale calibration for 0 mv to +10 mv input range*/ wait for rdy low /* wait for rdy pin to go low to indicate end of calibration cycle*/ /* the part has now completed self-calibration and is in idle mode*/ 1 this operation is not necessary if the default values of the filter register or the dac register are the values used in the app lication. table xx. pseudo-code for setting up ad7730 for continuous conversion and continuous read operation write 02 hex to serial port /* writes to communications register setting next operation as write to mode register*/ write 2180 hex to serial port /* writes to mode register starting continuous conversions for 0 mv to +10 mv input range*/ write 21 hex to serial port /* writes to communications register setting next operation as continuous read from data register*/ set din line of ad7730 low /* ensures part is not reset while in continuous read mode*/ read_data: wait for rdy low /* wait for rdy pin to go low to indicate output update*/ read 24-bit data from serial port /* read conversion result from ad7730's data register*/ loop to read_data until all data gathered write 30 hex to serial port /* ends continuous read operation and places part in mode where it expects write to communications register*/
ad7730/ad7730l C38C rev. a microcomputer/microprocessor interfacing the ad7730s flexible serial interface allows for easy interface to most microcomputers and microprocessors. the pseudo-code of table xix and table xx outline typical sequences for inter- facing a microcontroller or microprocessor to the ad7730. figures 20, 21 and 22 show some typical interface circuits. the serial interface on the ad7730 has the capability of operat- ing from just three wires and is compatible with spi interface protocols. the three-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system. register lengths on the ad7730 vary from 8 to 16 to 24 bits. the 8-bit serial ports of most microcontrollers can handle communication with these registers as either one, two or three 8-bit transfers. dsp processors and microprocessors generally transfer 16 bits of data in a serial data operation. some of these processors, such as the adsp-2105, have the facility to program the amount of cycles in a serial transfer. this allows the user to tailor the number of bits in any transfer to match the register length of the required register in the ad7730. in any case, writing 32 bits of data to a 24-bit register is not an issue provided the final eight bits of the word are all 1s. this is because the part returns to the communications register following a write operation. even though some of the registers on the ad7730 are only eight bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer if required. for example, if the dac register is to be updated, the processor must first write to the communica- tions register (saying that the next operation is a write to the mode register) and then write eight bits to the dac register. this can all be done in a single 16-bit transfer, if required, be- cause once the eight serial clocks of the write operation to the communications register have been completed, the part imme- diately sets itself up for a write operation to the dac register. ad7730 to 68hc11 interface figure 20 shows an interface between the ad7730 and the 68hc11 microcontroller. the diagram shows the minimum (three-wire) interface with cs on the ad7730 hardwired low. in this scheme, the rdy bit of the status register is monitored to determine when the data register is updated. an alternative scheme, which increases the number of interface lines to four, is to monitor the rdy output line from the ad7730. the moni- toring of the rdy line can be done in two ways. first, rdy can be connected to one of the 68hc11s port bits (such as pc0), which is configured as an input. this port bit is then polled to determine the status of rdy . the second scheme is to use an interrupt driven system, in which case the rdy output is con- nected to the irq input of the 68hc11. for interfaces which require control of the cs input on the ad7730, one of the port bits of the 68hc11 (such as pc1), which is configured as an output, can be used to drive the cs input. the 68hc11 is configured in the master mode with its cpol bit set to a logic zero and its cpha bit set to a logic one. when the 68hc11 is configured like this, its sclk line idles low between data transfers. therefore, the pol input of the ad7730 should be hardwired low. for systems where it is preferable that the sclk idle high, the cpol bit of the 68hc11 should be set to a logic 1 and the pol input of the ad7730 should be hard- wired to a logic high. the ad7730 is not capable of full duplex operation. if the ad7730 is configured for a write operation, no data appears on the data out lines even when the sclk input is active. when the ad7730 is configured for continuous read operation, data presented to the part on the data in line is monitored to determine when to exit the continuous read mode. sync reset ad7730 sclk data out data in cs pol ss sck miso mosi 68hc11 dv dd dv dd figure 20. ad7730 to 68hc11 interface ad7730 to 8051 interface an interface circuit between the ad7730 and the 8xc51 mi- crocontroller is shown in figure 21. the diagram shows the minimum number of interface connections with cs on the ad7730 hardwired low. in the case of the 8xc51 interface, the minimum number of interconnects is just two. in this scheme, the rdy bit of the status register is monitored to determine when the data register is updated. the alternative scheme, which increases the number of interface lines to three, is to monitor the rdy output line from the ad7730. the monitor- ing of the rdy line can be done in two ways. first, rdy can be connected to one of the 8xc51s port bits (such as p1.0), which is configured as an input. this port bit is then polled to deter- mine the status of rdy . the second scheme is to use an inter- rupt driven system, in which case the rdy output is connected to the int1 input of the 8xc51. for interfaces that require control of the cs input on the ad7730, one of the port bits of the 8xc51 (such as p1.1), which is configured as an output, can be used to drive the cs input. the 8xc51 is configured in its mode 0 serial interface mode. its serial interface contains a single data line. as a result, the data out and data in pins of the ad7730 should be connected together. this means that the ad7730 must not be
ad7730/ad7730l rev. a C39C configured for continuous read operation when interfacing to the 8xc51. the serial clock on the 8xc51 idles high between data transfers and therefore the pol input of the ad7730 should be hardwired to a logic high. the 8xc51 outputs the lsb first in a write operation while the ad7730 expects the msb first so the data to be transmitted has to be rearranged before being written to the output serial register. similarly, the ad7730 outputs the msb first during a read operation while the 8xc51 expects the lsb first. therefore, the data read into the serial buffer needs to be rearranged before the correct data word from the ad7730 is available in the accumulator. sync reset ad7730 pol data out data in sclk cs p3.0 p3.1 8xc51 dv dd figure 21. ad7730 to 8xc51 interface ad7730 to adsp-2103/adsp-2105 interface figure 22 shows an interface between the ad7730 and the adsp-2105 dsp processor. in the interface shown, the rdy bit of the status register is again monitored to determine when the data register is updated. the alternative scheme is to use an interrupt driven system, in which case the rdy output is connected to the irq2 input of the adsp-2105. the rfs and tfs pins of the adsp-2105 are configured as active low out- puts and the adsp-2105 serial clock line, sclk, is also config- ured as an output. the pol pin of the ad7730 is hardwired low. because the sclk from the adsp-2105 is a continuous clock, the cs of the ad7730 must be used to gate off the clock once the transfer is complete. the cs for the ad7730 is active when either the rfs or tfs outputs from the adsp-2105 are active. the serial clock rate on the adsp-2105 should be lim- ited to 3 mhz to ensure correct operation with the ad7730. sync reset ad7730 data out data in sclk cs dr sclk adsp-2105 dv dd rfs tfs dt pol figure 22. ad7730 to adsp-2105 interface
ad7730/ad7730l C40C rev. a applications the on-chip pga allows the ad7730 to handle analog input voltage ranges as low as 10 mv full scale. this allows the user to connect a transducer directly to the input of the ad7730. the ad7730 is primarily targeted for weigh-scale and load-cell applications. the majority of the applications have a strain- gage transducer whose resistance changes when subjected to mechanical stress. normally, the gages are configured in a wheat stone bridge arrangement. the strain gage is a passive device and requires an excitation voltage (or in some cases a current) to derive a voltage output. two types of voltage excita- tion can be provided for the bridge: dc excitation or ac excita- tion. these are discussed in the following sections. while the desire in most applications is to provide a single supply solution (something that is aided by the ad7730s single supply capabil- ity), some applications provide a bipolar excitation voltage in order to increase the output voltage from the bridge. in such cases, the input voltage applied to the ad7730 can be slightly negative with respect to ground. figure 23 shows how to config- ure the ad7730 to handle this type of input signal. dc excitation of bridge in dc-excitation applications, the excitation voltage provided for the bridge is a fixed dc voltage. connections between the ad7730 and the bridge are very straightforward in this type of applica- tion as illustrated in figure 23. the bridge configuration shown is a six-lead configuration with separate return leads for the reference lines. this allows a force/sense effect on the load cell excitation voltage, eliminating voltage drops caused by the exci- tation current flowing through the lead resistances. in applica- tions where the lead lengths are short, a four-wire configuration can be used with the excitation voltage and analog ground con- nected local to the ad7730s ref in(+) and ref in(C) termi- nals. illustrating a major advantage of the ad7730, the 5 v excitation voltage for the bridge can be used directly as the refer- ence voltage for the ad7730, eliminating the need for precision matched resistors in generating a scaled-down reference. the application is a ratiometric one with variations in the exci- tation voltage being reflected in variations in the analog input voltage and reference voltage of the ad7730. because the ad7730 is a truly ratiometric part, with the reference voltage and excitation voltages equal, it is possible to evaluate its total excitation voltage rejection. this is unlike other converters which give a separate indication of the rejection of reference, analog inputs and power supply. the combined (total) rejection for the ad7730 when moving the excitation voltage (which was also the power supply voltage) was better than 115 db when evaluated with a load cell simulator. drift considerations are a primary concern for load cell applica- tions. it is recommended for these applications that the ad7730 is operated in chop mode to accrue the benefits of the excel- lent drift performance of the part in chop mode. a common source of unwanted drift effects are parasitic thermocouples. thermocouple effects are generated every time there is a junc- tion of two dissimilar metals. all components in the signal path should be chosen to minimize thermocouple effects. ic sockets and link options should be avoided as much as possible. while it is impossible to remove all thermocouple effects, attempts should be made to equalize the thermocouples on each leg of the di fferen- tial input to minimize the differential voltage generated. figure 23. typical connections for dc-excited bridge application sigma- delta modulator av dd dv dd ad7730 6-bit dac serial interface and control logic register bank clock generation programmable digital filter sigma-delta a/d converter buffer pga ain2(+)/d1 ain2(C)/d0 acx acx standby sync mclk in mclk out sclk cs din dout reset rdy pol dgnd agnd mux ac excitation clock calibration microcontroller + in+ outC inC out+ ref in(+) ref in(C) ain1(+) ain1(C) excitation voltage = +5v +/C
ad7730/ad7730l rev. a C41C long lead lengths from the bridge to the ad7730 facilitate the pickup of mains frequency on the analog input, the reference input and the power supply. the analog inputs to the ad7730 are buffered, which allows the user to connect whatever noise reduction capacitors are necessary in the application. the ad7730 boasts excellent common-mode and normal- mode rejection of mains frequency on both the analog and reference inputs. in chop mode, care must be taken in choosing the output update rate so it does not result in reducing line frequency rejection (see digital filtering section). the input offset current on the ad7730 is 10 na maximum which results in a maxi- mum, dc offset voltage of 1.75 mv in a 350 w bridge applica- tion. care should taken with inserting large source impedances on the reference input pins as these inputs are not buffered and the source impedances can result in gain errors. in many load-cell applications, a portion of the dynamic range of the bridge output is consumed by a pan weight or tare weight. in such applications, the 6-bit tare dac of the ad7730 can be used to adjust out this tare weight as outlined previously. ac excitation of bridge ac excitation of the bridge addresses many of the concerns with thermocouple, offset and drift effects encountered in dc-excited applications. in ac-excitation, the polarity of the excitation volt- age to the bridge is reversed on alternate cycles. the result is the elimination of dc errors at the expense of a more complex sys- tem design. figure 24 outlines the connections for an ac-excited bridge application based on the ad7730. the excitation voltage to the bridge must be switched on alternate cycles. transistors t1 to t4 in figure 24 perform the switching of the excitation voltage. these transistors can be discrete matched bipolar or mos transistors, or a dedicated bridge driver chip such as the 4427 from micrel can be used to perform the task. since the analog input voltage and the reference voltage are reversed on alternate cycles, the ad7730 must be synchronized with this reversing of the excitation voltage. to allow the ad7730 to synchronize itself with this switching, it provides the logic control signals for the switching of the excitation voltage. these signals are the nonoverlapping cmos outputs acx and acx . one of the problems encountered with ac-excitation is the set- tling time associated with the analog input signals after the excitation voltage is switched. this is particularly true in appli- cations where there are long lead lengths from the bridge to the ad7730. it means that the converter could encounter errors because it is processing signals which are not fully settled. the ad7730 addresses this problem by allowing the user to program a delay of up to 48.75 m s between the switching of the acx signals and the processing of data at the analog inputs. this is achieved using the dl bits of the filter register. the ad7730 also scales the acx switching frequency in accor- dance with the output update rate. this avoids situations where the bridge is switched at an unnecessarily faster rate than the system requires. the fact that the ad7730 can handle reference voltages which are the same as the excitation voltages is particularly useful in ac-excitation where resistor divider arrangements on the reference input add to the settling time associated with the switching. figure 24. typical connections for ac-excited bridge application sigma- delta modulator av dd dv dd ad7730 6-bit dac serial interface and control logic register bank clock generation programmable digital filter sigma-delta a/d converter buffer pga ain2(+)/d1 ain2(C)/d0 acx acx standby sync mclk in mclk out sclk cs din dout reset rdy pol dgnd agnd mux ac excitation clock calibration microcontroller + in+ outC inC out+ ref in(+) ref in(C) ain1(+) ain1(C) excitation voltage = +5v t4 t3 t2 t1 +/C
ad7730/ad7730l C42C rev. a figure 25. ad7730 with bipolar excitation of the bridge bipolar excitation of the bridge as mentioned previously, some applications will require that the ad7730 handle inputs from a bridge that is excited by a bipolar voltage. the number of applications requiring this are limited, but with the addition of some external components the ad7730 is capable of handling such signals. figure 25 outlines one ap- proach to the problem. the example shown is a dc-excited bridge that is driven from 5 v supplies. in such a circuit, two issues must be addressed. the first is how to get the ad7730 to handle input voltages near or below ground and the second is how to take the 10 v excitation voltage which appears across the b ridge and generate a suitable reference voltage for the ad7730. the circuit of figure 25 attempts to address these two issues simultaneously. the ad7730s analog and digital supplies can be split such that av dd and dv dd can be at separate potentials and agnd and dgnd can also be at separate potentials. the only stipulation is that av dd or dv dd must not exceed the agnd by 5.5 v. in figure 25, the dv dd is operated at +3 v, wh ich allows the agnd to go down to C2.5 v with respect to system ground. this means that all logic signals to the part must not exceed 3 v with respect to system ground. the av dd is operated at +2.5 v with respect to system ground. the bridge is excited with 10 v across its inputs. the output of the bridge is biased around the midpoint of the excitation volt- ages which in this case is system ground or 0 v. in order for the common-mode voltage of the analog inputs to sit correctly, the agnd of the ad7730 must be biased below system ground by a minimum of 1.2 v. the 10 v excitation voltage must be re- duced to 5 v before being applied as the reference voltage for the ad7730. the resistor string r1, r2 and r3, takes the 10 v excitation voltage and generates differential voltage of nominally 5 v. amplifiers a1 and a2 buffer the resistor string voltages and provide the av dd and agnd voltages as well as the ref in(+) and ref in(C) voltages for the ad7730. the differential reference voltage for the part is +5 v. the ad7730 retains its ratiometric operation with this reference voltage varying in sym- pathy with the analog input voltage. the values of the resistors in the resistor string can be changed to allow a larger dv dd voltage. for example, if r1 = 3 k w , r2 = 10 k w and r3 = 7 k w , the av dd and agnd voltages become +3.5 v and C1.5 v respectively. this allows the ad7730 to be used with a +3.6 v dv dd voltage while still allowing the analog input range to be within the specified common-mode range. an alternate scheme to this is to generate the av dd and agnd voltages from regulators or zener diodes driven from the +5 v and C5 v supplies respectively. the reference voltage for the part would be generated in the same manner as just outlined but amplifiers a1 and a2 would not be required to buffer the volt- ages as they are now only driving the reference pins of the ad7730. however, care must be taken in this scheme to ensure that the ref in(+) voltage does not exceed av dd and that the ref in(C) voltage does not go below agnd. +5v C5v sigma- delta modulator dv dd ad7730 6-bit dac serial interface and control logic register bank clock generation programmable digital filter sigma-delta a/d converter buffer pga standby sync mclk in mclk out sclk cs din dout reset rdy pol dgnd mux calibration microcontroller + in+ outC inC out+ ref in(+) av dd ain1(+) ain1(C) system ground +3v a1 a2 +5v C5v +5v C5v r1 5k r2 10k r3 5k 1/2 op284 or 1/2 op213 1/2 op284 or 1/2 op213 ref in(C) agnd all voltage values are with respect to system ground. +/C
C43C appendix a ad7730l specifications
low power bridge transducer adc key features resolution of 110,000 counts (peak-to-peak) power consumption: 15 mw typ offset drift: < 1 ppm/ 8 c gain drift: 3 ppm/ 8 c line frequency rejection: >150 db buffered differential inputs programmable filter cutoffs specified for drift over time operates with reference voltages of 1 v to 5 v additional features two-channel programmable gain front end on-chip dac for offset/tare removal fast step mode ac or dc excitation single supply operation applications portable weigh scales functional block diagram * protected by u.s. patent no: 5, 134, 401. other patent applications filed. a appendixCad7730l* C44C general description the ad7730l is a complete low power analog front-end for weigh-scale and pressure measurement applications. the device accepts low level signals directly from a transducer and outputs a serial digital word. the input signal is applied to a proprietary programmable gain front end based around an analog modula- tor. the modulator output is processed by a low pass program- mable digital filter, allowing adjustment of filter cutoff, output rate and settling-time. the part features two buffered differential programmable gain analog inputs as well as a differential reference input. the part operates from a single +5 v supply and typically consumes less than 3 ma. it accepts four unipolar analog input ranges: 0 mv to +10 mv, +20 mv, +40 mv and +80 mv and four bipolar ranges 10 mv, 20 mv, 40 mv and 80 mv. the peak-to- peak resolution achievable directly from the part is 1 in 110,000 counts. an on-chip 6-bit dac allows the removal of tare voltages. clock signals for synchronizing ac excitation of the bridge are also provided. the serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. the ad7730l contains self-calibration and system calibration options and features an offset drift of less than 5 nv/ c and a gain drift of less than 3 ppm/ c. the part is available in a 24-lead soic and 24-lead tssop package. sigma- delta modulator ad7730l 6-bit dac serial interface and control logic register bank clock generation programmable digital filter sigma-delta a/d converter buffer pga 100na agnd 100na av dd vbias ain1(+) ain1(C) ain2(+)/d1 ain2(C)/d0 acx acx standby sync mclk in mclk out sclk cs din dout reset rdy pol dgnd agnd av dd dv dd ref in(C) ref in(+) mux reference detect ac excitation clock + C rev. a
C45C rev. a ad7730/ad7730l parameter b version 1 units conditions/comments static performance (chp = 1) no missing codes 2 24 bits min output noise and update rates 2 see tables xxi & xxii integral nonlinearity 22 ppm of fsr max offset error 2 see note 3 offset error and offset drift refer to both offset drift vs. temperature 2 5 nv/ c typ unipolar offset and bipolar zero errors offset drift vs. time 4 25 nv/1000 hours typ positive full-scale error 2, 5 see note 3 positive full-scale drift vs temp 2, 6, 7 3 ppm of fs/ c max positive full-scale drift vs time 4 10 ppm of fs/1000 hours typ gain error 2, 8 see note 3 gain drift vs. temperature 2, 6, 9 3 ppm/ c max gain drift vs. time 4 10 ppm/1000 hours typ bipolar negative full-scale error 2 see note 3 negative full-scale drift vs. temp 2, 6 3 ppm of fs/ c max power supply rejection 120 db typ measured with zero differential voltage common-mode rejection (cmr) 118 db min at dc. measured with zero differential voltage analog input dc bias current 2 40 na max analog input dc bias current drift 2 100 pa/ c typ analog input dc offset current 2 10 na max analog input dc offset current drift 2 50 pa/ c typ static performance (chp = 0) 2 no missing codes 24 bits min skip = 0 10 output noise and update rates see tables xxiii & xxiv integral nonlinearity 22 ppm of fsr max offset error see note 3 offset error and offset drift refer to both offset drift vs. temperature 6 0.5 m v/ c typ unipolar offset and bipolar zero errors offset drift vs. time 4 2.5 m v/1000 hours typ positive full-scale error 5 see note 3 positive full-scale drift vs. temp 6, 7 0.6 m v/ c typ positive full-scale drift vs. time 4 3 m v/1000 hours typ gain error 8 see note 3 gain drift vs. temperature 6, 9 2 ppm/ c typ gain drift vs. time 4 10 ppm/1000 hours typ bipolar negative full-scale error see note 3 negative full-scale drift vs. temp 0.6 m v/ c typ power supply rejection 90 db typ measured with zero differential voltage common-mode rejection (cmr) on ain 105 db typ at dc. measured with zero differential voltage cmr on ref in 100 db typ at dc. measured with zero differential voltage analog input dc bias current 50 na max analog input dc bias current drift 150 pa/ c typ analog input dc offset current 25 na max analog input dc offset current drift 75 pa/ c typ analog inputs/reference inputs normal-mode 50 hz rejection 2 88 db min from 49 hz to 51 hz normal-mode 60 hz rejection 2 88 db min from 59 hz to 61 hz common-mode 50 hz rejection 2 120 db min from 49 hz to 51 hz common-mode 60 hz rejection 2 120 db min from 59 hz to 61 hz analog inputs differential input voltage ranges 11 assuming 2.5 v or 5 v reference with hiref bit set appropriately 0 to +10 or 10 mv nom gain = 250 0 to +20 or 20 mv nom gain = 125 0 to +40 or 40 mv nom gain = 62.5 0 to +80 or 80 mv nom gain = 31.25 absolute/common-mode voltage 12 agnd + 1.2 v v min av dd C 0.95 v v max reference input ref in(+) C ref in(C) voltage +2.5 v nom hiref bit of mode register = 0 ref in(+) C ref in(C) voltage +5 v nom hiref bit of mode register = 1 absolute/common-mode voltage 13 agnd C 30 mv v min av dd + 30 mv v max no ref trigger voltage 0.3 v min no ref bit active if v ref below this voltage 0.65 v max no ref bit inactive if v ref above this voltage ad7730lCspecifications (av dd = +5 v, dv dd = +3 v or +5 v; ref in(+) = av dd ; ref in(C) = agnd = dgnd = 0 v; f clk in = 2.4576 mhz. all specifications t min to t max unless otherwise noted.)
C46C rev. a parameter b version 1 units conditions/comments logic inputs input current 10 m a max all inputs except sclk and mclk in v inl , input low voltage 0.8 v max dv dd = +5 v v inl , input low voltage 0.4 v max dv dd = +3 v v inh , input high voltage 2.0 v min sclk only (schmitt trigerred input) v t+ 1.4/3 v min to v max dv dd = +5 v v t+ 1/2.5 v min to v max dv dd = +3 v v tC 0.8/1.4 v min to v max dv dd = +5 v v tC 0.4/1.1 v min to v max dv dd = +3 v v t+ C v tC 0.4/0.8 v min to v max dv dd = +5 v v t+ C v tC 0.4/0.8 v min to v max dv dd = +3 v mclk in only v inl , input low voltage 0.8 v max dv dd = +5 v v inl , input low voltage 0.4 v max dv dd = +3 v v inh , input high voltage 3.5 v min dv dd = +5 v v inh , input high voltage 2.5 v min dv dd = +3 v logic outputs (including mclk out) v ol , output low voltage i sink = 800 m a except for mclk out 14 ; 0.4 v max v dd 15 = +5 v v ol , output low voltage i sink = 100 m a except for mclk out 14 ; 0.4 v max v dd 15 = +3 v v oh , output high voltage i source = 200 m a except for mclk out 14 ; 4.0 v min v dd 15 = +5 v v oh , output high voltage i source = 100 m a except for mclk out 14 ; v dd C 0.6 v v min v dd 15 = +3 v floating state leakage current 10 m a max floating state output capacitance 2 9 pf typ transducer burnout ain1(+) current C100 na nom ain1(C) current 100 na nom initial tolerance @ 25 c 10 % typ drift 2 0.1 %/ c typ offset (tare) dac resolution 6 bit lsb size 2.3/2.6 mv min/mv max 2.5 mv nominal with 5 v reference (ref in/2000) dac drift 16 3.5 ppm/ c max dac drift vs. time 4, 16 25 ppm/1000 hours typ differential linearity C0.25/+0.75 lsb max guaranteed monotonic system calibration positive full-scale calibration limit 17 1.05 fs v max fs is the nominal full-scale voltage (10 mv, 20 mv, 40 mv or 80 mv) negative full-scale calibration limit 17 C1.05 fs v max offset calibration limit 18 C1.05 fs v max input span 17 0.8 fs v min 2.1 fs v max power requirements power supply voltages av dd C agnd voltage +4.75 to +5.25 v min to v max dv dd voltage +2.7 to +5.25 v min to v max with agnd = 0 v power supply currents external mclk. digital i/ps = 0 v or dv dd av dd current (normal mode) 3.7 ma max all input ranges except 0 mv to +10 mv and 10 mv, typically 2.7 ma av dd current (normal mode) 5.5 ma max input ranges of 0 mv to +10 mv and 10 mv only, typically 4 ma dv dd current (normal mode) 0.45 ma max dv dd of 2.7 v to 3.3 v, typically 0.3 ma dv dd current (normal mode) 1 ma max dv dd of 4.75 v to 5.25 v, typically 0.75 ma av dd + dv dd current (standby mode) 21 m a max typically 13 m a. external mclk in = 0 v or dv dd power dissipation av dd = dv dd = +5 v. digital i/ps = 0 v or dv dd normal mode 23.5 mw max all input ranges except 0 mv to +10 mv and 10 mv, typically 15 mw 32.5 mw max input ranges of 0 mv to +10 mv and 10 mv only, typically 23.75 mw standby mode 105 m w max typically 65 m w. external mclk in = 0 v or dv dd ad7730/ad7730l
C47C rev. a ad7730/ad7730l notes 1 1 temperature range: C40 c to +85 c. 1 2 sample tested during initial release. 1 3 the offset (or zero) numbers with chp = 1 are typically 3 m v precalibration. internal zero-scale calibration reduces this by about 1 m v. offset numbers with chp = 0 can be up to 1 mv precalibration. internal zero-scale calibration reduces this to 2 m v typical. system zero-scale calibration reduces offset numbers with chp = 1 and chp = 0 to the order of the noise. gain errors can be up to 3000 ppm precalibration with chp = 0 and chp = 1. performing internal full-scale calibrations o n the 80 mv range reduces the gain error to less than 100 ppm for the 80 mv and 40 mv ranges, to about 250 ppm for the 20 mv range and to about 500 ppm on the 10 mv range. system ful l-scale calibration reduces this to the order of the noise. positive and negative full-scale errors can be calculated from the offset and gain errors. 1 4 these numbers are generated during life testing of the part. 1 5 positive full-scale error includes offset errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 1 6 recalibration at any temperature will remove these errors. 1 7 full-scale drift includes offset drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar i nput ranges. 1 8 gain error is a measure of the difference between the measured and the ideal span between any two points in the transfer functi on. the two points used to calculate the gain error are positive full scale and negative full scale. see terminology. 1 9 gain error drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 10 no missing codes performance with chp = 0 and skip = 1 is reduced below 24 bits for sf words lower than 180 decimal. 11 the analog input voltage range on the ain1(+) and ain2(+) inputs is given here with respect to the voltage on the ain1(C) and a in2(C) inputs respectively. 12 the common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 13 the common-mode voltage range on the reference input pair (ref in(+) and ref in(C)) applies provided the absolute input voltage specification is obeyed. 14 these logic output levels apply to the mclk out output only when it is loaded with a single cmos load. 15 v dd refers to dv dd for all logic outputs expect d0, d1, acx and acx where it refers to av dd . in other words, the output logic high for these four outputs is determined by av dd . 16 this number represents the total drift of the channel with a zero input and the dac output near full scale. 17 after calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. if the input is less tha n negative full scale, the device outputs all 0s. 18 these calibration and span limits apply provided the absolute input voltage specification is obeyed. the offset calibration lim it applies to both the unipolar zero point and the bipolar zero point. specifications subject to change without notice. timing characteristics 1, 2 limit at t min to t max parameter (b version) units conditions/comments master clock range 1 mhz min for specified performance 5 mhz max t 1 50 ns min sync pulsewidth t 2 50 ns min reset pulsewidth read operation t 3 0 ns min rdy to cs setup time t 4 0 ns min cs falling edge to sclk active edge setup time 3 t 5 4 0 ns min sclk active edge to data valid delay 3 60 ns max dv dd = +4.75 v to +5.25 v 80 ns max dv dd = +2.75 v to +3.3 v t 5a 4, 5 0 ns min cs falling edge to data valid delay 60 ns max dv dd = +4.75 v to +5.25 v 80 ns max dv dd = +2.7 v to +3.3 v t 6 100 ns min sclk high pulsewidth t 7 100 ns min sclk low pulsewidth t 8 0 ns min cs rising edge to sclk inactive edge hold time 3 t 9 6 10 ns min bus relinquish time after sclk inactive edge 3 80 ns max t 10 100 ns max sclk active edge to rdy high 3, 7 write operation t 11 0 ns min cs falling edge to sclk active edge setup time 3 t 12 30 ns min data valid to sclk edge setup time t 13 25 ns min data valid to sclk edge hold time t 14 100 ns min sclk high pulsewidth t 15 100 ns min sclk low pulsewidth t 16 0 ns min cs rising edge to sclk edge hold time notes 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of d v dd ) and timed from a voltage level of 1.6 v. 2 see figures 18 and 19. 3 sclk active edge is falling edge of sclk with pol = 1; sclk active edge is rising edge of sclk with pol = 0. 4 these numbers are measured with the load circuit of figure 1 and defined as the time required for the output to cross the v ol or v oh limits. 5 this specification only comes into play if cs goes low while sclk is low (pol = 1) or if cs goes low while sclk is high (pol = 0). it is primarily required for interfacing to dsp machines. 6 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the tim ing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 rdy returns high after the first read from the device after an output update. the same data can be read again, if required, while rdy is high, although care should be taken that subsequent reads do not occur close to the next output update. (av dd = +4.75 v to +5.25 v; dv dd = +3 v to +5.25 v; agnd = dgnd = 0 v; f clk in = 2.4576 mhz; input logic 0 = 0 v, logic 1 = dv dd unless otherwise noted).
ad7730/ad7730l C48C rev. a output noise and resolution specification the ad7730l can be programmed to operate in either chop mode or nonchop mode. the chop mode can be enabled in ac-excited or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications . these options are discussed in more detail in earlier sections. the chop mode has the advantage of lower drift numbers and better noi se immunity, but the noise is approximately 20% higher for a given C3 db frequency and output data rate. it is envisaged that the major- ity of weigh-scale users of the ad7730l will operate the part in chop mode to avail themselves of the excellent drift performan ce and noise immunity when chopping is enabled. the following tables outline the noise performance of the part in both chop and noncho p modes over all input ranges for a selection of output rates. output noise (chp = 1) this mode is the primary mode of operation of the device. table xxi shows the output rms noise for some typical output update rates and C3 db frequencies for the ad7730 when used in chopping mode (chp of filter register = 1) with a master clock frequency of 2.4576 mhz. these numbers are typical and are generated at a differential analog input voltage of 0 v. the output update rate is selected via the sf0 to sf11 bits of the filter register. table xxii, meanwhile, shows the output peak-to-peak r esolu- tion in counts for the same output update rates. the numbers in brackets are the effective peak-to-peak resolution in bits (rou nded to the nearest 0.5 lsb). it is important to note that the numbers in table xxii represent the resolution for which there will be n o code flicker within a six-sigma limit. they are not calculated based on rms noise, but on peak-to-peak noise. the numbers are generated for the bipolar input ranges. when the part is operated in unipolar mode, the output noise will be th e same as the equivalent bipolar input range. as a result, the numbers in table xxi will remain the same for unipolar ranges whil e the numbers in table ii will change. to calculate the numbers for table xxii for unipolar input ranges simply divide the peak-to-pe ak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits. table xxi. output noise vs. input range and update rate (chp = 1) typical output rms noise in nv output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 25 hz 0.98 hz 2048 920 ms 120 ms 245 140 105 70 50 hz 1.97 hz 1024 460 ms 60 ms 340 220 160 100 75 hz 2.96 hz 683 306 ms 40 ms 420 270 170 110 100 hz* 3.95 hz 512 230 ms 30 ms 500 290 180 130 200 hz 7.9 hz 256 115 ms 15 ms 650 490 280 165 *power-on default table xxii. peak-to-peak resolution vs. input range and update rate (chp = 1) peak-to-peak resolution in counts (bits) output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 25 hz 0.98 hz 2048 920 ms 120 ms 110k (17) 94k (16.5) 64k (16) 46k (15.5) 50 hz 1.97 hz 1024 460 ms 60 ms 80k (16.5) 60k (16) 42k (15.5) 33k (15) 75 hz 2.96 hz 683 306 ms 40 ms 62k (16) 50k (15.5) 39k (15) 31k (15) 100 hz* 3.95 hz 512 230 ms 30 ms 53k (15.5) 46k (15.5) 36k (15) 25k (14.5) 200 hz 7.9 hz 256 115 ms 15 ms 44k (15.5) 27k (15) 24k (14.5) 20k (14.5) *power-on default output noise (chp = 0) table xxiii shows the output rms noise for some typical output update rates and C3 db frequencies for the ad7730l when used in nonchopping mode (chp of filter register = 0) with a master clock frequency of 2.4576 mhz. these numbers are typical and are generated at a differential analog input voltage of 0 v. the output update rate is selected via the sf0 to sf11 bits of the fil ter regis- ter. table xxiv, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. the numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 lsb). it is important to note that the n umbers in table xxiv represent the resolution for which there will be no code flicker within a six-sigma limit. they are not calculated b ased on rms noise, but on peak-to-peak noise. the numbers are generated for the bipolar input ranges. when the part is operated in unipolar mode, the output noise will be th e same as the equivalent bipolar input range. as a result, the numbers in table xxiii will remain the same for unipolar ranges wh ile the numbers in table xxiv will change. to calculate the number for table xxiv for unipolar input ranges simply divide the peak- to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.
ad7730/ad7730l rev. a C49C table xxiii. output noise vs. input range and update rate (chp = 0) typical output rms noise in nv output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 75 hz 2.9 hz 2048 332 ms 53.2 ms 320 215 135 100 100 hz 3.9 hz 1536 250 ms 40 ms 325 245 160 110 150 hz 5.85 hz 1024 166 ms 26.6 ms 410 275 180 130 300 hz 11.7 hz 512 83 ms 13.3 ms 590 370 265 180 600 hz 23.4 hz 256 41.6 ms 6.6 ms 910 580 350 220 table xxiv. peak-to-peak resolution vs. input range and update rate (chp = 0) peak-to-peak resolution in counts (bits) output C3 db sf settling time settling time input range input range input range input range data rate frequency word normal mode fast mode = 6 80 mv = 6 40 mv = 6 20 mv = 6 10 mv 75 hz 2.9 hz 2048 332 ms 53.2 ms 85k (16.5) 62k (16) 49k (15.5) 33k (15) 100 hz 3.9 hz 1536 250 ms 40 ms 82k (16.5) 55k (15.5) 42k (15.5) 30k (15) 150 hz 5.85 hz 1024 166 ms 26.6 ms 65k (16) 48k (15.5) 36k (15) 25k (14.5) 300 hz 11.7 hz 512 83 ms 13.3 ms 45k (15.5) 36k (15) 25k (14.5) 18k (14) 600 hz 23.4 hz 256 41.6 ms 6.63 ms 30k (15) 23k (14.5) 19k (14) 15k (14)
ad7730/ad7730l C50C rev. a page index topic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 ad7730 specifications . . . . . . . . . . . . . . . . . . . . . . . . 2 timing characteristics . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . 5 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 detailed functional block diagram . . . . . . . 6 signal processing chain . . . . . . . . . . . . . . . . . . . . . 7 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin function description . . . . . . . . . . . . . . . . . . . 7 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 output noise and resolution specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 on-chip registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 summary of on-chip registers . . . . . . . . . . . . . . . . . . . . 12 communications register . . . . . . . . . . . . . . . . . . . . . . . . 13 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dac register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 offset calibration register . . . . . . . . . . . . . . . . . . . . . . . . 20 gain calibration register . . . . . . . . . . . . . . . . . . . . . . . . . 20 test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 reading from and writing to the on-chip registers. . . . . . . . . . . . . . . . . . . . . . . . . . 21 calibration operation summary . . . . . . . . . . . 22 circuit description . . . . . . . . . . . . . . . . . . . . . . . . 23 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 analog input channels . . . . . . . . . . . . . . . . . . . . . . . . . . 24 analog input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 bipolar/unipolar inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 24 burnout currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 reference detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 sigma-delta modulator . . . . . . . . . . . . . . . . . . . . 26 digital filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 first stage filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 second stage filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 internal zero-scale calibration . . . . . . . . . . . . . . . . . . . . 30 internal full-scale calibration . . . . . . . . . . . . . . . . . . . . . 30 system zero-scale calibration . . . . . . . . . . . . . . . . . . . . . 31 system full-scale calibration . . . . . . . . . . . . . . . . . . . . . 31 span and offset limits . . . . . . . . . . . . . . . . . . . . . . . . . . 31 power-up and calibration . . . . . . . . . . . . . . . . . . . . . . . . 32 drift considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 using the ad7730 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 clocking and oscillator circuit . . . . . . . . . . . . . . . . . . . . 32 system synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 33 single-shot conversions . . . . . . . . . . . . . . . . . . . . . . . . . 33 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 evaluating the ad7730 performance . . . . . . . . . . . . . . . . 34 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 configuring the ad7730 . . . . . . . . . . . . . . . . . . . . . 37 microcomputer/microprocessor interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ad7730 to 68hc11 interface . . . . . . . . . . . . . . . . . . . . . 38 ad7730 to 8051 interface . . . . . . . . . . . . . . . . . . . . . . . . 38 ad7730 to adsp-2105 interface . . . . . . . . . . . . . . . . . . 39 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 dc excitation of bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ac excitation of bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 41 bipolar excitation of bridge . . . . . . . . . . . . . . . . . . . . . . . 42 appendix aCad7730l specifications . . . . . . . . . . 43 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 51 table index table title page table i. output noise vs. input range and update rate (chp = 1) 10 table ii. peak-to-peak resolution vs. input range and update rate (chp = 1) 10 table iii. output noise vs. input range and update rate (chp = 0) 11 table iv. peak-to-peak resolution vs. input range and update rate (chp = 0) 11 table v. summary of on-chip registers 12 table vi. communications register 13 table vii. read/write mode 13 table viii. register selection 14 table ix. status register 14 table x. mode register 15 table xi. operating modes 15 table xii. input range selection 17 table xiii. channel selection 18 table xiv. filter register 18 table xv. sf ranges 19 table xvi. dac register 20 table xvii. calibration operations 22 table xviii. reset events 23 table xix. pseudo-code for initiating a self-calibration after power-on/reset 37 table xx. pseudo-code for setting up ad7730 for continuous conversion and continuous read operation 37 table xxi. output noise vs. input range and update rate (chp = 1) 48 table xxii. peak-to-peak resolution vs. input range and update rate (chp = 1) 48 table xxiii. output noise vs. input range and update rate (chp = 0) 49 table xxiv. peak-to-peak resolution vs. input range and update rate (chp = 0) 49
ad7730/ad7730l rev. a C51C outline dimensions dimensions shown in inches and (mm). plastic dip (n-24) thin shrink small outline (ru-24) small outline (r-24) 24 112 13 0.280 (7.11) 0.240 (6.10) pin 1 1.275 (32.30) 1.125 (28.60) 0.150 (3.81) min 0.200 (5.05) 0.125 (3.18) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 24 13 12 1 0.311 (7.90) 0.303 (7.70) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
C52C c3269C8C1/98 printed in u.s.a.

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